3.3V LVDS 1-Bit High Speed Differential Receiver

General Description This single receiver is designed for high speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology. The receiver translates LVDS levels, with a typical differential input threshold of 100 mV, to LVTTL signal levels. LVDS provides low EMI at ultra low

3.3V LVDS 1-Bit High Speed Differential Receiver

文件：1.14464 Mbytes Page：10 Pages

封装/外壳：8-SOIC（0.154"，3.90mm 宽） 包装：管件 描述：IC RECEIVER 0/1 8SOIC 集成电路（IC） 驱动器，接收器，收发器

3.3V LVDS 1-Bit High Speed Differential Receiver

General Description This single receiver is designed for high speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology. The receiver translates LVDS levels, with a typical differential input threshold of 100 mV, to LVTTL signal levels. LVDS provides low EMI at ultra low

3.3V LVDS 1-Bit High Speed Differential Receiver

文件：1.14464 Mbytes Page：10 Pages

封装/外壳：8-SOIC（0.154"，3.90mm 宽） 包装：卷带（TR） 描述：IC RECEIVER 0/1 8SOIC 集成电路（IC） 驱动器，接收器，收发器

Type KX Thermocouple, 1 Pr #16 Sol, PVC Ins Yel, Red, OS, Yellow PVC Jkt, 300V PLTC ITC CMG

Product Description Type KX Thermocouple, 1 Pair 16AWG (Solid) Chromel+Alumel, PVC Insulation Yel, Red Color Code, Overall Beldfoil® Shield, Yellow PVC Outer Jacket, PLTC ITC CMG AWM 2464 SUN RES

5Vdc or 3.3Vdc TTL / CMOSAND SINE WAVE TEMPERATURE-COMPENSATED XTAL OSCILLATORS

FEATURES: • Compatible with 14 pin dual in line. • Tight stability available. • Compact size. • Low current consumption. APPLICATIONS: • Cellular and cordless phones. • Reference clock. • Facsimile and computer control. • Communication equipment.

HDSL MAGNETICS

文件：61.11 Kbytes Page：2 Pages

SM BATTERY HOLDER 2/3A, ON TAPE

文件：210.04 Kbytes Page：1 Pages

10 TO 1000 MHz TO-8 CASCADABLE AMPLIFIERS

文件：161.29 Kbytes Page：2 Pages