GENERAL DESCRIPTION

The XRT83SL314 is a fully integrated 14-channel short-haul line interface unit (LIU) that operates from a single 3.3V power supply. Using internal termination, the LIU provides one bill of materials to operate in T1, E1, or J1 mode independently on a per channel basis with minimum external components.

FEATURES

• Fully integrated 14-Channel short haul transceivers for T1/J1 (1.544MHz) and E1 (2.048MHz) applications.

• T1/E1/J1 short haul and clock rate are per port selectable through software without changing components.

• Internal Impedance matching on both receive and transmit for 75Ω (E1), 100Ω (T1), 110Ω (J1), and 120Ω (E1) applications are per port selectable through software without changing components.

• Power down on a per channel basis with independent receive and transmit selection.

• Five pre-programmed transmit pulse settings for T1 short haul applications.

• Arbitrary Pulse Generators for both T1 and E1 modes.

• On-Chip transmit short-circuit protection and limiting protects line drivers from damage on a per channel basis.

• Independent Crystal-Less digital jitter attenuators (JA) with 32-Bit or 64-Bit FIFO for the receive and transmit paths

• On-Chip frequency multiplier generates T1 or E1 master clocks from a variety of external clock sources (8, 16, 56, 64, 128, 256kHz and 1X, 2X, 4X, 8X T1 or E1)

• Driver failure monitor output (DMO) alerts of possible system or external component problems.

• Transmit outputs and receive inputs may be High impedance for protection or redundancy applications on a per channel basis.

• Support for automatic protection switching.

• 1:1 and 1+1 protection without relays.

• Receive monitor mode handles 0 to 29dB resistive attenuation (flat loss) along with 0 to 6dB cable loss for both T1 and E1.• Receiver line attenuation indication output in 1dB steps.

• Loss of signal (RLOS) according to ITU-T G.775/ ETS300233 (E1) and ANSI T1.403 (T1/J1).

• Programmable receive slicer threshold (45, 50, 55, or 68) for improved receiver interference immunity.

• Programmable data stream muting upon RLOS detection.

• On-Chip HDB3/B8ZS encoder/decoder with an internal 16-bit LCV counter for each channel.

• On-Chip digital clock recovery circuit for high input jitter tolerance.

• QRSS pattern generator and detection for testing and monitoring.

• Error and bipolar violation insertion and detection.

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APPLICATIONS

• T1 Digital Cross Connects (DSX-1)

• ISDN Primary Rate Interface

• CSU/DSU E1/T1/J1 Interface

• T1/E1/J1 LAN/WAN Routers

• Public Switching Systems and PBX Interfaces

• T1/E1/J1 Multiplexer and Channel Banks

• Integrated Multi-Service Access Platforms (IMAPs)

• Integrated Access Devices (IADs)

• Inverse Multiplexing for ATM (IMA)

• Wireless Base Stations