[Nanya]

DESCRIPTION

This is a family of 4,194,304 x 4 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory cells within the same row. Power supply voltage (+5.0V ), refresh cycle (2K Ref), access time (-5 or -6), power consumption (Normal or Low power) and package type (SOJ) are optional features of this family.

FEATURES

• Fast Page Mode operation .

• TTL(5V) compatible inputs and outputs

• Single +5V ± 10 power supply

• JEDEC Standard pinout

• CAS before RAS refresh, hidden refresh, RAS -only refresh capability

• Refresh : 2048 cycles / 32 ms

• Self-refresh capability (L-ver only)

• Multi-bit test mode capability

• Available in plastic SOJ packages