Features

70mA open-collector drive for

SERDATN

Low capacitive loading

Discriminates SERCLK into

single-phase chip clock output

Separates data and start blts for

both recelve and transmit

Provides single bus load for

multiple VMSbus controllers

Simplifies controller design and

allows use of slower technology

VMEbus receilver for SYSCLK

VMEbus driver/recelver for

SYSRESETN

16-pin DIP