Description

The HM5425161B, the HM5425801B and the HM5425401B are the Double Data Rate (DDR) SDRAM devices. Read and write operations are performed at the cross points of the CLK and the CLK. This high speed data transfer is realized by the 2-bit prefetch piplined architecture. Data strobe (DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode resistor, the on-chip Delay Locked Loop (DLL) can be set enable or disable.

Features

• 2.5 V power supply

• SSTL-2 interface for all inputs and outputs

• Clock frequency: 143 MHz/133 MHz/125 MHz/100 MHz (max)

• Data inputs, outputs, and DM are synchronized with DQS

• 4 banks can operate simultaneously and independently

• Burst read/write operation

• Programmable burst length: 2/4/8

- Burst read stop capability

• Programmable burst sequence

- Sequential

- Interleave

• Start addressing capability

- Even and Odd

• Programmable CAS latency: 2/2.5

• 8192 refresh cycles: 7.8 µs (64 ms/8192 cycles)

• 2 variations of refresh

- Auto refresh

- Self refresh