Description

The EDS2508AP is a 256M bits SDRAM organized as 8,388,608 words × 8 bits × 4 banks. The EDS2516AP is a 256M bits SDRAM organized as 4194304 words × 16 bits × 4 banks. All inputs and outputs are referred to the rising edge of the clock input. It is packaged in standard 60-ball µBGA®.

Features

• 3.3V power supply

• Clock frequency: 133MHz (max.)

• LVTTL interface

• Single pulsed /RAS

• 4 banks can operate simultaneously and independently

• Burst read/write operation and burst read/single write operation capability

• Programmable burst length (BL): 1, 2, 4, 8, full page

• 2 variations of burst sequence

- Sequential (BL = 1, 2, 4, 8)

- Interleave (BL = 1, 2, 4, 8)

• Programmable /CAS latency (CL): 2, 3

• Byte control by DQM

: DQM (EDS2508AP)

: UDQM, LDQM (EDS2516AP)

• Refresh cycles: 8192 refresh cycles/64ms

• 2 variations of refresh

- Auto refresh

- Self refresh