LC2MOS Signal Conditioning ADC

GENERAL DESCRIPTION The AD7712 is a complete analog front end for low frequency measurement applications. The device has two analog input channels and accepts either low level signals directly from a transducer or high level (±4
VREF) signals, and outputs a serial digital word. It employs a sig

LC2MOS Signal Conditioning ADC

文件：258.99 Kbytes Page：28 Pages

LC2MOS Signal Conditioning ADC

文件：258.99 Kbytes Page：28 Pages

Signal Conditioning ADC

文件：304.15 Kbytes Page：29 Pages

Low-dropout three-pin voltage regulator 1.2-A type

■Overview The AN7700, AN7700F, and AN7700SP series are stabilized constant-voltage power supplies with small difference between I/O voltages (0.5 V typ.). They are suitable for low-voltage, battery-driven equipment, and home appliances and industrial equipment with great fluctuation of the s

Low-dropout three-pin voltage regulator 1.2-A type

■Overview The AN7700, AN7700F, and AN7700SP series are stabilized constant-voltage power supplies with small difference between I/O voltages (0.5 V typ.). They are suitable for low-voltage, battery-driven equipment, and home appliances and industrial equipment with great fluctuation of the s

Low-dropout three-pin voltage regulator 1.2-A type

■Overview The AN7700, AN7700F, and AN7700SP series are stabilized constant-voltage power supplies with small difference between I/O voltages (0.5 V typ.). They are suitable for low-voltage, battery-driven equipment, and home appliances and industrial equipment with great fluctuation of the s

Wireless LAN Baseband Controller

DESCRIPTION The MSM7712 is the first release in a series of wireless LAN baseband controllers, designated .XI (a suffix of the IEEE P802.11 protocol). The MSM7712 integrates the baseband physical layer and the lower MAC layers into a single IC that supports specific draft standards of the P802.11

Sound effects DSP

GENERAL DESCRIPTION The SAA7712H provides for digital signal processing power in TV systems and home theatre systems. A DSP core is equipped with digital inputs and outputs, a 5-band parametric equalizer accelerator, a digital co-processor interface and a delay line memory. This architecture ac