Embedded Programmable Logic Device

General Description Altera FLEX 10KE devices are enhanced versions of FLEX 10K devices. Based on reconfigurable CMOS SRAM elements, the FLEX architecture incorporates all features necessary to implement common gate array megafunctions. With up to 200,000 typical gates, FLEX 10KE devices provide t

1. Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet

The Altera enhanced configuration device is a single-device, high-speed, advanced configuration solution for very high-density FPGAs. The core of an enhanced configuration device is divided into two major blocks, a configuration controller and a flash memory. The flash memory is used to store conf

Embedded Programmable Logic Device

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Embedded Programmable Logic Device

General Description\nAltera FLEX 10KE devices are enhanced versions of FLEX 10K devices. Based on reconfigurable CMOS SRAM elements, the FLEX architecture incorporates all features necessary to implement common gate array megafunctions. With up to 200,000 typical gates, FLEX 10KE devices provide the – MultiVoltTM I/O pins can drive or be driven by 2.5-V, 3.3-V, or 5.0-V devices\n– Low power consumption\n– Bidirectional I/O performance (tSUand tCO) up to 212 MHz\n– Fully compliant with the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2for 3.3-V operation at 33 MHz;

可编程逻辑器件(CPLD/FPGA)

封装/外壳：484-BBGA 包装：托盘 描述：IC FPGA 369 I/O 484FBGA 集成电路（IC） FPGA（现场可编程门阵列）

可编程逻辑器件(CPLD/FPGA)

封装/外壳：240-BFQFP 裸露焊盘 包装：托盘 描述：IC FPGA 182 I/O 240RQFP 集成电路（IC） FPGA（现场可编程门阵列）

Embedded Programmable Logic Device

General Description Altera FLEX 10KE devices are enhanced versions of FLEX 10K devices. Based on reconfigurable CMOS SRAM elements, the FLEX architecture incorporates all features necessary to implement common gate array megafunctions. With up to 200,000 typical gates, FLEX 10KE devices provide t

1. Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet

The Altera enhanced configuration device is a single-device, high-speed, advanced configuration solution for very high-density FPGAs. The core of an enhanced configuration device is divided into two major blocks, a configuration controller and a flash memory. The flash memory is used to store conf