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EP1C6Q400

Cyclone FPGA Family

文件:1.14233 Mbytes Page:94 Pages

ALTERA

阿尔特

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

ALTERA

阿尔特

Section I. Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

ALTERA

阿尔特

Section I. Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

ALTERA

阿尔特

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

ALTERA

阿尔特

Section I. Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

ALTERA

阿尔特

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

ALTERA

阿尔特

Section I. Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

ALTERA

阿尔特

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

ALTERA

阿尔特

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

ALTERA

阿尔特

Section I. Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

ALTERA

阿尔特

Section I. Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

ALTERA

阿尔特

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

ALTERA

阿尔特

Cyclone FPGA Family

文件:1.14233 Mbytes Page:94 Pages

ALTERA

阿尔特

Cyclone FPGA Family

文件:1.14233 Mbytes Page:94 Pages

ALTERA

阿尔特

Cyclone FPGA Family

文件:1.3576 Mbytes Page:106 Pages

ALTERA

阿尔特

Cyclone FPGA Family

文件:1.14233 Mbytes Page:94 Pages

ALTERA

阿尔特

Cyclone FPGA Family

文件:1.3576 Mbytes Page:106 Pages

ALTERA

阿尔特

Cyclone FPGA Family

文件:1.14233 Mbytes Page:94 Pages

ALTERA

阿尔特

Cyclone FPGA Family

文件:1.14233 Mbytes Page:94 Pages

ALTERA

阿尔特

Cyclone FPGA Family

文件:1.14233 Mbytes Page:94 Pages

ALTERA

阿尔特

Cyclone FPGA Family

文件:1.3576 Mbytes Page:106 Pages

ALTERA

阿尔特

Cyclone FPGA Family

文件:1.14233 Mbytes Page:94 Pages

ALTERA

阿尔特

Cyclone FPGA Family

文件:1.14233 Mbytes Page:94 Pages

ALTERA

阿尔特

Cyclone FPGA Family

文件:1.3576 Mbytes Page:106 Pages

ALTERA

阿尔特

Cyclone FPGA Family

文件:1.14233 Mbytes Page:94 Pages

ALTERA

阿尔特

Cyclone FPGA Family

文件:1.14233 Mbytes Page:94 Pages

ALTERA

阿尔特

Cyclone FPGA Family

文件:1.3576 Mbytes Page:106 Pages

ALTERA

阿尔特

Cyclone FPGA Family

文件:1.14233 Mbytes Page:94 Pages

ALTERA

阿尔特

Cyclone FPGA Family

文件:1.14233 Mbytes Page:94 Pages

ALTERA

阿尔特

Cyclone FPGA Family

文件:1.3576 Mbytes Page:106 Pages

ALTERA

阿尔特

更新时间:2026-3-17 20:00:00
IC供应商 芯片型号 品牌 批号 封装 库存 备注 价格
ALTERA/阿尔特拉
2026+
NA
65248
百分百原装现货 实单必成
ALTERA
24+
QFP
6980
原装现货,可开13%税票
ALTERA
2021+
QFP
8630
主营《XILINX》《ALTERA》品牌
ALTERA
20+
QFP
500
样品可出,优势库存欢迎实单
ALT
24+
15
ALTERA
23+
QFP
4500
中国领先的ALTERA嵌入式专业分销商!原装正品!
专订ALTERA
QFP
2350
一级代理 原装正品假一罚十价格优势长期供货
ALTERA
11+
NA
2310
全新原装
ALTERA/阿尔特拉
23+
NA
2310
原装正品代理渠道价格优势
ALTERA/INTEL
2021
BGA
1000
全新、原装

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