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位置：首页 > IC中文资料第466页 > EP1C6Q

EP1C6Q价格

参考价格：￥226.8482

型号：EP1C6Q240C6N 品牌：Altera 备注：这里有EP1C6Q多少钱，2025年最近7天走势，今日出价，今日竞价，EP1C6Q批发/采购报价，EP1C6Q行情走势销售排行榜，EP1C6Q报价。
型号 功能描述 生产厂家 企业 LOGO 操作
EP1C6

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

EP1C6

Cyclone Series Device Thermal Resistance

Cyclone III Device Family Overview Cyclone® III device family offers a unique combination of high functionality, low power and low cost. Based on Taiwan Semiconductor Manufacturing Company (TSMC) low-power (LP) process technology, silicon optimizations and software features to minimize power cons

Altera

阿尔特

EP1C6

1. Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet

The Altera enhanced configuration device is a single-device, high-speed, advanced configuration solution for very high-density FPGAs. The core of an enhanced configuration device is divided into two major blocks, a configuration controller and a flash memory. The flash memory is used to store conf

Altera

阿尔特

EP1C6

Cyclone FPGA Family

文件：1.14233 Mbytes Page：94 Pages

Altera

阿尔特

EP1C6Q100C6ES

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

EP1C6Q100C7ES

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

EP1C6Q100C8ES

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

EP1C6Q100I6ES

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

EP1C6Q100I7ES

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

EP1C6Q100I8ES

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

EP1C6Q144C6ES

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

EP1C6Q144C7ES

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

EP1C6Q144C8ES

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

EP1C6Q144I6ES

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

EP1C6Q144I7ES

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

EP1C6Q144I8ES

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

EP1C6Q240C6ES

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

EP1C6Q240C7ES

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

EP1C6Q240C8ES

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

EP1C6Q240C8N

Supports configuration through low-cost serial configuration device

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

EP1C6Q240I6ES

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

EP1C6Q240I7ES

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

EP1C6Q240I8ES

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

EP1C6Q256C6ES

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

EP1C6Q256C7ES

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

EP1C6Q256C8ES

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

EP1C6Q256I6ES

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

EP1C6Q256I7ES

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

EP1C6Q256I8ES

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

EP1C6Q324C6ES

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

EP1C6Q324C7ES

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

EP1C6Q324C8ES

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

EP1C6Q324I6ES

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

EP1C6Q324I7ES

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

EP1C6Q324I8ES

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

EP1C6Q400C6ES

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

EP1C6Q400C6ES

Section I. Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

EP1C6Q400C7ES

Section I. Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

EP1C6Q400C7ES

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

EP1C6Q400C8ES

Section I. Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

EP1C6Q400C8ES

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

EP1C6Q400I6ES

Section I. Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

EP1C6Q400I6ES

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

EP1C6Q400I7ES

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

EP1C6Q400I7ES

Section I. Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

EP1C6Q400I8ES

Section I. Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

EP1C6Q400I8ES

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

EP1C6Q100C6

Cyclone FPGA Family

文件：1.14233 Mbytes Page：94 Pages

Altera

阿尔特

EP1C6Q100C7

Cyclone FPGA Family

文件：1.14233 Mbytes Page：94 Pages

Altera

阿尔特

EP1C6Q100C8

Cyclone FPGA Family

文件：1.14233 Mbytes Page：94 Pages

Altera

阿尔特

EP1C6Q100I6

Cyclone FPGA Family

文件：1.14233 Mbytes Page：94 Pages

Altera

阿尔特

EP1C6Q100I7

Cyclone FPGA Family

文件：1.14233 Mbytes Page：94 Pages

Altera

阿尔特

EP1C6Q100I8

Cyclone FPGA Family

文件：1.14233 Mbytes Page：94 Pages

Altera

阿尔特

EP1C6Q144C6

Cyclone FPGA Family

文件：1.14233 Mbytes Page：94 Pages

Altera

阿尔特

EP1C6Q144C7

Cyclone FPGA Family

文件：1.14233 Mbytes Page：94 Pages

Altera

阿尔特

EP1C6Q144C8

Cyclone FPGA Family

文件：1.14233 Mbytes Page：94 Pages

Altera

阿尔特

EP1C6Q144I6

Cyclone FPGA Family

文件：1.14233 Mbytes Page：94 Pages

Altera

阿尔特

EP1C6Q144I7

Cyclone FPGA Family

文件：1.14233 Mbytes Page：94 Pages

Altera

阿尔特

EP1C6Q144I8

Cyclone FPGA Family

文件：1.14233 Mbytes Page：94 Pages

Altera

阿尔特

EP1C6Q240C6

Cyclone FPGA Family

文件：1.14233 Mbytes Page：94 Pages

Altera

阿尔特

EP1C6Q产品属性

  • 类型

    描述

  • 型号

    EP1C6Q

  • 功能描述

    FPGA - 现场可编程门阵列 FPGA - Cyclone I 598 LABs 185 IOs

  • RoHS

    否

  • 制造商

    Altera Corporation

  • 系列

    Cyclone V E

  • 逻辑块数量

    943 内嵌式块RAM -

  • EBR

    1956 kbit

  • 输入/输出端数量

    128

  • 最大工作频率

    800 MHz

  • 工作电源电压

    1.1 V

  • 最大工作温度

    + 70 C

  • 安装风格

    SMD/SMT

  • 封装/箱体

    FBGA-256

EP1C6Q供应商更多...

更新时间：2025-12-27 11:35:00
IC供应商 芯片型号 品牌 批号 封装 库存 备注 价格
深圳市恒达亿科技有限公司
EP1C6T144C8N
alterA
25+
QFP-144
3500
100%公司原装正品,价格优势,敬请来电! 产品相片 144-LQFP 产品培训模块 Three Reasons to Use FPGA’’’’s in Industrial Designs 标准包装 180 类别 集成电路 (IC) 家庭 嵌入式 - FPGA(现场可编程门阵列) 系列 Cyclone
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深圳市纳艾斯科技有限公司
EP1C6Q240I7N
专订ALTER
24+
QFP
8000
只做自己库存,全新原装进口正品假一赔百,可开13%增
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深圳市毅创腾电子科技有限公司
EP1C6Q240C8N
ALTERA
QFP
8600
专业分销全系列产品!绝对原装正品!量大可订!价格优
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深圳市勤思达科技有限公司
EP1C6T144C6N
alterA
12+
TQFP144
5000
深圳市勤思达科技有限公司主营alterA系列全新原装正品,公司现货供应EP1C6T144C6N,欢迎咨询洽谈。
询价
深圳市威尔健半导体有限公司
EP1C6Q240C8N
ALTERA/阿尔特拉
23+
BGA
18098
终端可以免费供样,支持BOM配单!
询价
深圳市毅创辉电子科技有限公司
EP1C6F256C6N
ALTERA
23+
BGA
4000
原装正品公司现货
询价
深圳市力拓辉电子有限公司
EP1C6T144C8N
ALTERA
21+
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5000
全新原装 鄙视假货
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深圳市科恒伟业电子有限公司
EP1C6Q240C8N
ALTERA
2450+
LQFP
6584
只做原装正品假一赔十为客户做到零风险!!
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深圳市星佑电子有限公司
EP1C6F256C8N
alterA
12+
BGA256
1000
深圳星佑电子代理alterA全系列产品 保证原厂原装正品价格便宜型号齐全订购电话:0755-83997861 0755-83266716
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深圳市昌和盛利电子有限公司
EP1C6Q240C8N
alterA
24+
PQFP240
12000
询价

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