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位置：首页 > IC中文资料 > EP1C6Q

EP1C6Q价格

参考价格：￥226.8482

型号：EP1C6Q240C6N 品牌：Altera 备注：这里有EP1C6Q多少钱，2026年最近7天走势，今日出价，今日竞价，EP1C6Q批发/采购报价，EP1C6Q行情走势销售排行榜，EP1C6Q报价。
型号 功能描述 生产厂家 企业 LOGO 操作
EP1C6Q100C6ES

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

ALTERA

阿尔特

EP1C6Q100C7ES

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

ALTERA

阿尔特

EP1C6Q100C8ES

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

ALTERA

阿尔特

EP1C6Q100I6ES

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

ALTERA

阿尔特

EP1C6Q100I7ES

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

ALTERA

阿尔特

EP1C6Q100I8ES

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

ALTERA

阿尔特

EP1C6Q144C6ES

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

ALTERA

阿尔特

EP1C6Q144C7ES

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

ALTERA

阿尔特

EP1C6Q144C8ES

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

ALTERA

阿尔特

EP1C6Q144I6ES

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

ALTERA

阿尔特

EP1C6Q144I7ES

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

ALTERA

阿尔特

EP1C6Q144I8ES

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

ALTERA

阿尔特

EP1C6Q240C6ES

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

ALTERA

阿尔特

EP1C6Q240C6N

EP1C6Q240C6N - 芯片, FPGA, CYCLONE, 5980单元, 240PQFP

The EP1C6Q240C6N is a Cyclone® FPGA based on a 1.5V, 0.13µm features all-layer copper SRAM process with densities up to 5980 logic elements (LEs) and up to 92160-bits of RAM. With features like phaselocked loops (PLLs) for clocking and a dedicated double data rate (DDR) interface to meet DDR SDRAM a ·Supports configuration through low-cost serial configuration device\n·Supports for LVTTL, LVCMOS, SSTL-2 and SSTL-3 I/O standards\n·High-speed (640Mbps) LVDS I/O support\n·Low-speed (311Mbps) LVDS I/O support\n·311Mbps RSDS I/O support\n·Up to two PLLs per device provide clock multiplication and ph;

INTEL

英特尔

EP1C6Q240C7ES

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

ALTERA

阿尔特

EP1C6Q240C8ES

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

ALTERA

阿尔特

EP1C6Q240C8N

Supports configuration through low-cost serial configuration device

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

ALTERA

阿尔特

EP1C6Q240I6ES

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

ALTERA

阿尔特

EP1C6Q240I7ES

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

ALTERA

阿尔特

EP1C6Q240I8ES

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

ALTERA

阿尔特

EP1C6Q256C6ES

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

ALTERA

阿尔特

EP1C6Q256C7ES

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

ALTERA

阿尔特

EP1C6Q256C8ES

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

ALTERA

阿尔特

EP1C6Q256I6ES

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

ALTERA

阿尔特

EP1C6Q256I7ES

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

ALTERA

阿尔特

EP1C6Q256I8ES

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

ALTERA

阿尔特

EP1C6Q324C6ES

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

ALTERA

阿尔特

EP1C6Q324C7ES

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

ALTERA

阿尔特

EP1C6Q324C8ES

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

ALTERA

阿尔特

EP1C6Q324I6ES

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

ALTERA

阿尔特

EP1C6Q324I7ES

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

ALTERA

阿尔特

EP1C6Q324I8ES

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

ALTERA

阿尔特

EP1C6Q400C6ES

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

ALTERA

阿尔特

EP1C6Q400C6ES

Section I. Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

ALTERA

阿尔特

EP1C6Q400C7ES

Section I. Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

ALTERA

阿尔特

EP1C6Q400C7ES

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

ALTERA

阿尔特

EP1C6Q400C8ES

Section I. Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

ALTERA

阿尔特

EP1C6Q400C8ES

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

ALTERA

阿尔特

EP1C6Q400I6ES

Section I. Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

ALTERA

阿尔特

EP1C6Q400I6ES

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

ALTERA

阿尔特

EP1C6Q400I7ES

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

ALTERA

阿尔特

EP1C6Q400I7ES

Section I. Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

ALTERA

阿尔特

EP1C6Q400I8ES

Section I. Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

ALTERA

阿尔特

EP1C6Q400I8ES

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

ALTERA

阿尔特

EP1C6Q100C6

Cyclone FPGA Family

文件：1.14233 Mbytes Page：94 Pages

ALTERA

阿尔特

EP1C6Q100C7

Cyclone FPGA Family

文件：1.14233 Mbytes Page：94 Pages

ALTERA

阿尔特

EP1C6Q100C8

Cyclone FPGA Family

文件：1.14233 Mbytes Page：94 Pages

ALTERA

阿尔特

EP1C6Q100I6

Cyclone FPGA Family

文件：1.14233 Mbytes Page：94 Pages

ALTERA

阿尔特

EP1C6Q100I7

Cyclone FPGA Family

文件：1.14233 Mbytes Page：94 Pages

ALTERA

阿尔特

EP1C6Q100I8

Cyclone FPGA Family

文件：1.14233 Mbytes Page：94 Pages

ALTERA

阿尔特

EP1C6Q144C6

Cyclone FPGA Family

文件：1.14233 Mbytes Page：94 Pages

ALTERA

阿尔特

EP1C6Q144C7

Cyclone FPGA Family

文件：1.14233 Mbytes Page：94 Pages

ALTERA

阿尔特

EP1C6Q144C8

Cyclone FPGA Family

文件：1.14233 Mbytes Page：94 Pages

ALTERA

阿尔特

EP1C6Q144I6

Cyclone FPGA Family

文件：1.14233 Mbytes Page：94 Pages

ALTERA

阿尔特

EP1C6Q144I7

Cyclone FPGA Family

文件：1.14233 Mbytes Page：94 Pages

ALTERA

阿尔特

EP1C6Q144I8

Cyclone FPGA Family

文件：1.14233 Mbytes Page：94 Pages

ALTERA

阿尔特

EP1C6Q240C6

Cyclone FPGA Family

文件：1.14233 Mbytes Page：94 Pages

ALTERA

阿尔特

EP1C6Q240C6N

封装/外壳：240-BFQFP 包装：托盘 描述：IC FPGA 185 I/O 240QFP 集成电路（IC） FPGA（现场可编程门阵列）

INTEL

英特尔

EP1C6Q240C7

封装/外壳：240-BFQFP 包装：托盘 描述：IC FPGA 185 I/O 240QFP 集成电路（IC） FPGA（现场可编程门阵列）

INTEL

英特尔

EP1C6Q240C7

Cyclone FPGA Family

文件：1.14233 Mbytes Page：94 Pages

ALTERA

阿尔特

EP1C6Q产品属性

  • 类型

    描述

EP1C6Q供应商更多...

更新时间：2026-5-24 14:10:00
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