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EP1C3价格

参考价格：￥127.8018

型号：EP1C3T100C6N 品牌：Altera 备注：这里有EP1C3多少钱，2025年最近7天走势，今日出价，今日竞价，EP1C3批发/采购报价，EP1C3行情走势销售排行榜，EP1C3报价。

型号	功能描述	生产厂家企业	LOGO
EP1C3	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3	Cyclone Series Device Thermal Resistance Cyclone III Device Family Overview Cyclone® III device family offers a unique combination of high functionality, low power and low cost. Based on Taiwan Semiconductor Manufacturing Company (TSMC) low-power (LP) process technology, silicon optimizations and software features to minimize power cons	Altera 阿尔特	Altera
EP1C3	1. Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet The Altera enhanced configuration device is a single-device, high-speed, advanced configuration solution for very high-density FPGAs. The core of an enhanced configuration device is divided into two major blocks, a configuration controller and a flash memory. The flash memory is used to store conf	Altera 阿尔特	Altera
EP1C3	This datasheet describes enhanced configuration (EPC) devices 文件：621.91 Kbytes Page：36 Pages	Altera 阿尔特	Altera
EP1C3	Package Information Datasheet for Mature Altera Devices 文件：2.06334 Mbytes Page：182 Pages	Altera 阿尔特	Altera
EP1C3	Enhanced Configuration (EPC) Devices Datasheet 文件：633.77 Kbytes Page：36 Pages	Altera 阿尔特	Altera
EP1C3	Package Information Datasheet for Mature Altera Devices 文件：2.063429 Mbytes Page：182 Pages	Altera 阿尔特	Altera
EP1C3	Cyclone Device Handbook, Volume 1 文件：5.60108 Mbytes Page：385 Pages	ETCList of Unclassifed Manufacturers 未分类制造商	ETC
EP1C3	Cyclone FPGA Family 文件：1.14233 Mbytes Page：94 Pages	Altera 阿尔特	Altera
EP1C3F100C6ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F100C7ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F100C8ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F100I6ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F100I7ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F100I8ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F144C6ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F144C7ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F144C8ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F144I6ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F144I7ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F144I8ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F240C6ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F240C7ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F240C8ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F240I6ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F240I7ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F240I8ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F256C6ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F256C7ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F256C8ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F256I6ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F256I7ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F256I8ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F324C6ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F324C7ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F324C8ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F324I6ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F324I7ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F324I8ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F400C6ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F400C6ES	Section I. Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F400C7ES	Section I. Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F400C7ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F400C8ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F400C8ES	Section I. Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F400I6ES	Section I. Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F400I6ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F400I7ES	Section I. Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F400I7ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F400I8ES	Section I. Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F400I8ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3Q100C6ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3Q100C7ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3Q100C8ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3Q100I6ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3Q100I7ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3Q100I8ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3Q144C6ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3Q144C7ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3Q144C8ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera

EP1C3产品属性

类型
描述
型号
EP1C3
制造商
ALTERA
制造商全称
Altera Corporation
功能描述
1. Enhanced Configuration Devices(EPC4, EPC8, and EPC16) Data Sheet

EP1C3供应商更多...

更新时间：2025-12-28 14:22:00

IC供应商	芯片型号	品牌	批号	封装	库存	备注	价格
深圳市得捷芯城科技有限公司	EP1C3T100C6	ALTERA(阿尔特拉)	24+	标准封装	9663	我们只是原厂的搬运工	询价
深圳市纳艾斯科技有限公司	EP1C3T144I7N	专订ALTER	24+	QFP	8000	只做自己库存,全新原装进口正品假一赔百,可开13%增	询价
中天科工半导体（深圳）有限公司	EP1C3T144C8N	ALTERA/阿尔特拉	25+	TQFP144	32000	ALTERA/阿尔特拉全新特价EP1C3T144C8N即刻询购立享优惠#长期有货	询价
深圳市卓越微芯电子有限公司	EP1C3T100I7N	ALTERA	25+	QFP100	155	百分百原装正品真实公司现货库存本公司只做原装可	询价
深圳市正纳电子有限公司	EP1C3T100C8N	ALTERA	23+	QFP	10000	□原装进口价格好实需详询□□□□QQ350053121	询价
深圳市金华微盛电子有限公司	EP1C3T10017N	ALTERA	19+	BGA	14900		询价
深圳市亿智腾科技有限公司	EP1C3T144C8N	原厂原包	24+	原装	16739	原装进口现货,工厂客户可以放款。17377264928微信同	询价
深圳市勤思达科技有限公司	EP1C3T144I7N	alterA	12+	QFP-144	5000	深圳市勤思达科技有限公司主营alterA系列全新原装正品,公司现货供应EP1C3T144I7N,欢迎咨询洽谈。	询价
深圳市毅创腾电子科技有限公司	EP1C3T144C8N	ALTERA		QFP-144	3200	专业分销全系列产品!绝对原装正品!量大可订!价格优	询价
深圳航星空电子技术有限公司	EP1C3T100C8N	ALTERA	19+	QFP	3000		询价

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EP1C3规格书下载地址

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