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EP1C3价格

参考价格：￥127.8018

型号：EP1C3T100C6N 品牌：Altera 备注：这里有EP1C3多少钱，2025年最近7天走势，今日出价，今日竞价，EP1C3批发/采购报价，EP1C3行情走势销售排行榜，EP1C3报价。

型号	功能描述	生产厂家企业	LOGO
EP1C3	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3	Cyclone Series Device Thermal Resistance Cyclone III Device Family Overview Cyclone® III device family offers a unique combination of high functionality, low power and low cost. Based on Taiwan Semiconductor Manufacturing Company (TSMC) low-power (LP) process technology, silicon optimizations and software features to minimize power cons	Altera 阿尔特	Altera
EP1C3	1. Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet The Altera enhanced configuration device is a single-device, high-speed, advanced configuration solution for very high-density FPGAs. The core of an enhanced configuration device is divided into two major blocks, a configuration controller and a flash memory. The flash memory is used to store conf	Altera 阿尔特	Altera
EP1C3	This datasheet describes enhanced configuration (EPC) devices 文件：621.91 Kbytes Page：36 Pages	Altera 阿尔特	Altera
EP1C3	Cyclone Device Handbook, Volume 1 文件：5.60108 Mbytes Page：385 Pages	etc2List of Unclassifed Manufacturers etc未分类制造商etc2未分类制造商	etc2
EP1C3	Package Information Datasheet for Mature Altera Devices 文件：2.06334 Mbytes Page：182 Pages	Altera 阿尔特	Altera
EP1C3	Package Information Datasheet for Mature Altera Devices 文件：2.063429 Mbytes Page：182 Pages	Altera 阿尔特	Altera
EP1C3	Enhanced Configuration (EPC) Devices Datasheet 文件：633.77 Kbytes Page：36 Pages	Altera 阿尔特	Altera
EP1C3	Cyclone FPGA Family 文件：1.14233 Mbytes Page：94 Pages	Altera 阿尔特	Altera
EP1C3F100C6ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F100C7ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F100C8ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F100I6ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F100I7ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F100I8ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F144C6ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F144C7ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F144C8ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F144I6ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F144I7ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F144I8ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F240C6ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F240C7ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F240C8ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F240I6ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F240I7ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F240I8ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F256C6ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F256C7ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F256C8ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F256I6ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F256I7ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F256I8ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F324C6ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F324C7ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F324C8ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F324I6ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F324I7ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F324I8ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F400C6ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F400C6ES	Section I. Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F400C7ES	Section I. Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F400C7ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F400C8ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F400C8ES	Section I. Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F400I6ES	Section I. Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F400I6ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F400I7ES	Section I. Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F400I7ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F400I8ES	Section I. Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3F400I8ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3Q100C6ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3Q100C7ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3Q100C8ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3Q100I6ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3Q100I7ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3Q100I8ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3Q144C6ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3Q144C7ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera
EP1C3Q144C8ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	Altera 阿尔特	Altera

EP1C3产品属性

类型
描述
型号
EP1C3
制造商
ALTERA
制造商全称
Altera Corporation
功能描述
1. Enhanced Configuration Devices(EPC4, EPC8, and EPC16) Data Sheet

EP1C3供应商更多...

更新时间：2025-9-26 9:09:00

IC供应商	芯片型号	品牌	批号	封装	库存	备注	价格
深圳市恒达亿科技有限公司	EP1C324C8	ALTERA	25+	BGA	3200	全新原装、诚信经营、公司现货销售	询价
深圳市能元时代电子有限公司	EP1C324C8	ALTERA	23+	STOCK	39975	##公司主营品牌长期供应100%原装现货可含税提供技术	询价
深圳市智连鑫科技有限公司	EP1C3T100	ALTERA(阿尔特拉)	24+	N/A	4000	原厂原装现货订货价格优势终端BOM表可配单提供样品	询价
中天科工半导体（深圳）有限公司	EP1C3T144C8N	ALTERA/阿尔特拉	25+	TQFP144	32000	ALTERA/阿尔特拉全新特价EP1C3T144C8N即刻询购立享优惠#长期有货	询价
瑞航达科技(深圳)有限公司	EP1C3T100I7N	ALTERA			102	原装正品	询价
上海磐岳电子有限公司	EP1C324C8	ALTERA	2023+		1000	绝对全新原装,现货热卖	询价
深圳市勤思达科技有限公司	EP1C3T144I7N	alterA	12+	QFP-144	5000	深圳市勤思达科技有限公司主营alterA系列全新原装正品,公司现货供应EP1C3T144I7N,欢迎咨询洽谈。	询价
上海凌岳电子科技有限公司（上海涵恩科技）	EP1C324C8	ALTERA	2023+		3000	进口原装现货	询价
深圳市亿芯微电子有限公司	EP1C3T144C8N	ATREL	2020	QFP	493	原装假一赔十/DD	询价
深圳市威尔健半导体有限公司	EP1C3T144C8N	ALTERA/阿尔特拉	23+	DIP24	18098	终端可以免费供样,支持BOM配单!	询价

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EP1C3规格书下载地址

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