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EP1C20价格

参考价格：￥1068.4456

型号：EP1C20F324C6 品牌：ALT 备注：这里有EP1C20多少钱，2026年最近7天走势，今日出价，今日竞价，EP1C20批发/采购报价，EP1C20行情走势销售排行榜，EP1C20报价。

型号	功能描述	生产厂家企业	LOGO
EP1C20	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	ALTERA 阿尔特	ALTERA
EP1C20	Cyclone Series Device Thermal Resistance Cyclone III Device Family Overview Cyclone® III device family offers a unique combination of high functionality, low power and low cost. Based on Taiwan Semiconductor Manufacturing Company (TSMC) low-power (LP) process technology, silicon optimizations and software features to minimize power cons	ALTERA 阿尔特	ALTERA
EP1C20	1. Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet The Altera enhanced configuration device is a single-device, high-speed, advanced configuration solution for very high-density FPGAs. The core of an enhanced configuration device is divided into two major blocks, a configuration controller and a flash memory. The flash memory is used to store conf	ALTERA 阿尔特	ALTERA
EP1C20	Enhanced Configuration (EPC) Devices Datasheet 文件：633.77 Kbytes Page：36 Pages	ALTERA 阿尔特	ALTERA
EP1C20	Package Information Datasheet for Mature Altera Devices 文件：2.06334 Mbytes Page：182 Pages	ALTERA 阿尔特	ALTERA
EP1C20	Cyclone Device Handbook, Volume 1 文件：5.60108 Mbytes Page：385 Pages	ETCList of Unclassifed Manufacturers 未分类制造商	ETC
EP1C20	Package Information Datasheet for Mature Altera Devices 文件：2.063429 Mbytes Page：182 Pages	ALTERA 阿尔特	ALTERA
EP1C20	Cyclone FPGA Family 文件：1.14233 Mbytes Page：94 Pages	ALTERA 阿尔特	ALTERA
EP1C20	This datasheet describes enhanced configuration (EPC) devices 文件：621.91 Kbytes Page：36 Pages	ALTERA 阿尔特	ALTERA
EP1C20F100C6ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	ALTERA 阿尔特	ALTERA
EP1C20F100C7ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	ALTERA 阿尔特	ALTERA
EP1C20F100C8ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	ALTERA 阿尔特	ALTERA
EP1C20F100I6ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	ALTERA 阿尔特	ALTERA
EP1C20F100I7ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	ALTERA 阿尔特	ALTERA
EP1C20F100I8ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	ALTERA 阿尔特	ALTERA
EP1C20F144C6ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	ALTERA 阿尔特	ALTERA
EP1C20F144C7ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	ALTERA 阿尔特	ALTERA
EP1C20F144C8ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	ALTERA 阿尔特	ALTERA
EP1C20F144I6ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	ALTERA 阿尔特	ALTERA
EP1C20F144I7ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	ALTERA 阿尔特	ALTERA
EP1C20F144I8ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	ALTERA 阿尔特	ALTERA
EP1C20F240C6ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	ALTERA 阿尔特	ALTERA
EP1C20F240C7ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	ALTERA 阿尔特	ALTERA
EP1C20F240C8ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	ALTERA 阿尔特	ALTERA
EP1C20F240I6ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	ALTERA 阿尔特	ALTERA
EP1C20F240I7ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	ALTERA 阿尔特	ALTERA
EP1C20F240I8ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	ALTERA 阿尔特	ALTERA
EP1C20F256C6ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	ALTERA 阿尔特	ALTERA
EP1C20F256C7ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	ALTERA 阿尔特	ALTERA
EP1C20F256C8ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	ALTERA 阿尔特	ALTERA
EP1C20F256I6ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	ALTERA 阿尔特	ALTERA
EP1C20F256I7ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	ALTERA 阿尔特	ALTERA
EP1C20F256I8ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	ALTERA 阿尔特	ALTERA
EP1C20F324C6ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	ALTERA 阿尔特	ALTERA
EP1C20F324C7ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	ALTERA 阿尔特	ALTERA
EP1C20F324C8ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	ALTERA 阿尔特	ALTERA
EP1C20F324I6ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	ALTERA 阿尔特	ALTERA
EP1C20F324I7ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	ALTERA 阿尔特	ALTERA
EP1C20F324I8ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	ALTERA 阿尔特	ALTERA
EP1C20F400C6ES	Section I. Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	ALTERA 阿尔特	ALTERA
EP1C20F400C6ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	ALTERA 阿尔特	ALTERA
EP1C20F400C7ES	Section I. Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	ALTERA 阿尔特	ALTERA
EP1C20F400C7ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	ALTERA 阿尔特	ALTERA
EP1C20F400C8ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	ALTERA 阿尔特	ALTERA
EP1C20F400C8ES	Section I. Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	ALTERA 阿尔特	ALTERA
EP1C20F400I6ES	Section I. Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	ALTERA 阿尔特	ALTERA
EP1C20F400I6ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	ALTERA 阿尔特	ALTERA
EP1C20F400I7ES	Section I. Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	ALTERA 阿尔特	ALTERA
EP1C20F400I7ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	ALTERA 阿尔特	ALTERA
EP1C20F400I8ES	Section I. Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	ALTERA 阿尔特	ALTERA
EP1C20F400I8ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	ALTERA 阿尔特	ALTERA
EP1C20Q100C6ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	ALTERA 阿尔特	ALTERA
EP1C20Q100C7ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	ALTERA 阿尔特	ALTERA
EP1C20Q100C8ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	ALTERA 阿尔特	ALTERA
EP1C20Q100I6ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	ALTERA 阿尔特	ALTERA
EP1C20Q100I7ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	ALTERA 阿尔特	ALTERA
EP1C20Q100I8ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	ALTERA 阿尔特	ALTERA
EP1C20Q144C6ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	ALTERA 阿尔特	ALTERA
EP1C20Q144C7ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	ALTERA 阿尔特	ALTERA
EP1C20Q144C8ES	Cyclone FPGA Family Data Sheet Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)	ALTERA 阿尔特	ALTERA

EP1C20产品属性

类型
描述
型号
EP1C20
制造商
ALTERA
制造商全称
Altera Corporation
功能描述
1. Enhanced Configuration Devices(EPC4, EPC8, and EPC16) Data Sheet

EP1C20供应商更多...

更新时间：2026-3-2 17:33:00

IC供应商	芯片型号	品牌	批号	封装	库存	备注	价格
深圳市富达微科技有限公司	EP1C20F324	ALTERA(阿尔特拉)	24+	N/A	4000	原厂原装，价格优势，欢迎洽谈！	询价
深圳市祥瑞智科技有限公司	EP1C20F400C8N	ALTERA	25+	BGA	1250	原装现货特价热卖!!!0755-83210901	询价
深圳市华睿芯科技有限公司	EP1C20F324I7	ALTERA/阿尔特拉	24+	BGA	5000	全新原厂原装，进口正品现货，需要请联系电话：18675544552（微信同号）	询价
深圳市得捷芯城科技有限公司	EP1C20F324C7N	ALTERA(阿尔特拉)	25+	标准封装	6863	我们只是原厂的搬运工	询价
深圳市能元时代电子有限公司	EP1C20F324	ALTERA	23+	BGA	39932	##公司主营品牌长期供应100%原装现货可含税提供技术	询价
深圳市赛美科科技有限公司	EP1C20F24	专订ALTERA			2350	一级代理原装正品假一罚十价格优势长期供货	询价
深圳市正纳电子有限公司	EP1C20F324	ALTERA(阿尔特拉)	23+	NA	20094	正纳10年以上分销经验原装进口正品做服务做口碑有支持	询价
深圳市赛特兴科技有限公司	EP1C20F324	ALTERA(阿尔特拉)	23+	标准封装	4000	正规渠道,只有原装!	询价
深圳市毅创腾电子科技有限公司	EP1C20F400I8N	ALTERA		BGA	4200	专业分销全系列产品!绝对原装正品!量大可订!价格优	询价
深圳市恒创达实业有限公司	EP1C20C400C8	ALTERA/INTEL	2021	BGA	1000	全新、原装	询价

EP1C20芯片相关品牌

EP1C20规格书下载地址

EP1C20参数引脚图相关

EP1C20数据表相关新闻

EP1C20F324C8N
EP1C20F324C8N芯片是一款高性能、低功耗的可编程FPGA芯片，具有丰富的可编程逻辑资源、高速计算能力、通信接口和内部存储资源。它适用于各种需要定制化和高性能计算的应用场景，如数字逻辑设计、信号处理、通信系统等。
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EP1C12F324C7进口原装，主营军工级IC
EP1AGX60DF780C6N原装正品 ADI，NXP(恩智浦) ， XILINX(赛灵思) ，ALTERA（阿尔特拉），军工级IC专业优势渠道
2019-11-6
EP1C3T144C8N原装现货
EP1C3T144C8N原装现货
2019-10-24

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