型号 功能描述 生产厂家 企业 LOGO 操作
EP1C12T400

Cyclone FPGA Family

文件:1.14233 Mbytes Page:94 Pages

Altera

阿尔特

Section I. Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

Section I. Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

Section I. Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

Section I. Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

Section I. Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

Section I. Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

Altera

阿尔特

Cyclone FPGA Family

文件:1.14233 Mbytes Page:94 Pages

Altera

阿尔特

Cyclone FPGA Family

文件:1.14233 Mbytes Page:94 Pages

Altera

阿尔特

Cyclone FPGA Family

文件:1.3576 Mbytes Page:106 Pages

Altera

阿尔特

Cyclone FPGA Family

文件:1.14233 Mbytes Page:94 Pages

Altera

阿尔特

Cyclone FPGA Family

文件:1.14233 Mbytes Page:94 Pages

Altera

阿尔特

Cyclone FPGA Family

文件:1.3576 Mbytes Page:106 Pages

Altera

阿尔特

Cyclone FPGA Family

文件:1.14233 Mbytes Page:94 Pages

Altera

阿尔特

Cyclone FPGA Family

文件:1.3576 Mbytes Page:106 Pages

Altera

阿尔特

Cyclone FPGA Family

文件:1.14233 Mbytes Page:94 Pages

Altera

阿尔特

Cyclone FPGA Family

文件:1.14233 Mbytes Page:94 Pages

Altera

阿尔特

Cyclone FPGA Family

文件:1.14233 Mbytes Page:94 Pages

Altera

阿尔特

Cyclone FPGA Family

文件:1.3576 Mbytes Page:106 Pages

Altera

阿尔特

Cyclone FPGA Family

文件:1.14233 Mbytes Page:94 Pages

Altera

阿尔特

Cyclone FPGA Family

文件:1.14233 Mbytes Page:94 Pages

Altera

阿尔特

Cyclone FPGA Family

文件:1.3576 Mbytes Page:106 Pages

Altera

阿尔特

Cyclone FPGA Family

文件:1.14233 Mbytes Page:94 Pages

Altera

阿尔特

Cyclone FPGA Family

文件:1.3576 Mbytes Page:106 Pages

Altera

阿尔特

Cyclone FPGA Family

文件:1.14233 Mbytes Page:94 Pages

Altera

阿尔特

EP1C12T400产品属性

  • 类型

    描述

  • 型号

    EP1C12T400

  • 制造商

    ALTERA

  • 制造商全称

    Altera Corporation

  • 功能描述

    Cyclone FPGA Family

更新时间:2025-11-20 16:00:00
IC供应商 芯片型号 品牌 批号 封装 库存 备注 价格
ALTERA/INTEL
2021
BGA
1000
全新、原装
ALT
6000
面议
19
BGA
ALTERA
23+
BGA
5000
原装正品,假一罚十
ALTERA
2021+
QFP
8630
主营《XILINX》《ALTERA》品牌
JANPAN
16+
QFP
4000
进口原装现货/价格优势!
ALTERA(阿尔特拉)
24+
N/A
4000
原厂原装现货订货价格优势终端BOM表可配单提供样品
xilinx
25+
XILINX
6800
Intel FPGAs/Altera
23+
-
7300
专注配单,只做原装进口现货
ALTERA
2023+
QFP
5800
进口原装,现货热卖
ALTREA
25+
BGA
6500
独立分销商 公司只做原装 诚心经营 免费试样正品保证

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