2GB Unbuffered DDR2 SDRAM DIMM

2GB Unbuffered DDR2 SDRAM DIMM EBE21EE8ABFA (256M words ×72 bits, 2 Ranks) Features • Double-data-rate architecture; two data transfers per clock cycle • The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture • Bi-directional differential data strob

2GB Unbuffered DDR2 SDRAM DIMM

2GB Unbuffered DDR2 SDRAM DIMM\nEBE21EE8ABFA (256M words ×72 bits, 2 Ranks) • Double-data-rate architecture; two data transfers per clock cycle\n• Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver\n• Differential clock inputs (CK and /CK)\n• Commands entered on each positive CK edge; data and data mas;

2GB Unbuffered DDR2 SDRAM DIMM

2GB Unbuffered DDR2 SDRAM DIMM EBE21EE8ABFA (256M words ×72 bits, 2 Ranks) Features • Double-data-rate architecture; two data transfers per clock cycle • The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture • Bi-directional differential data strob

2GB Unbuffered DDR2 SDRAM DIMM

2GB Unbuffered DDR2 SDRAM DIMM EBE21EE8ABFA (256M words ×72 bits, 2 Ranks) Features • Double-data-rate architecture; two data transfers per clock cycle • The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture • Bi-directional differential data strob

2GB Unbuffered DDR2 SDRAM DIMM

2GB Unbuffered DDR2 SDRAM DIMM EBE21EE8ABFA (256M words ×72 bits, 2 Ranks) Features • Double-data-rate architecture; two data transfers per clock cycle • The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture • Bi-directional differential data strob

2GB Unbuffered DDR2 SDRAM DIMM

2GB Unbuffered DDR2 SDRAM DIMM EBE21EE8ABFA (256M words ×72 bits, 2 Ranks) Features • Double-data-rate architecture; two data transfers per clock cycle • The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture • Bi-directional differential data strob

2GB Unbuffered DDR2 SDRAM DIMM

Features • Double-data-rate architecture; two data transfers per clock cycle • The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture • Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver •

2GB Unbuffered DDR3 SDRAM DIMM

文件：208.18 Kbytes Page：18 Pages

2GB Unbuffered DDR3 SDRAM DIMM

文件：208.18 Kbytes Page：18 Pages

2GB Unbuffered DDR3 SDRAM DIMM

文件：208.18 Kbytes Page：18 Pages

2GB Unbuffered DDR3 SDRAM DIMM

文件：207.9 Kbytes Page：18 Pages