丝印代码：EB32882A；28-Bit to 56-Bit Registered Buffer With Address Parity Test One Pair to Four Pair Differential Clock PLL Driver

1FEATURES • 1-to-2 Register Outputs and 1-to-4 Clock Pair Outputs Support Stacked DDR3 RDIMMs • CKE Powerdown Mode for Optimized System Power Consumption • 1.5V/1.35V/1.25V Phase Lock Loop Clock Driver for Buffering One Differential Clock Pair (CK and CK) and Distributing to Four Different

丝印代码：EB32882A；28-Bit to 56-Bit Registered Buffer With Address Parity Test One Pair to Four Pair Differential Clock PLL Driver

1FEATURES • 1-to-2 Register Outputs and 1-to-4 Clock Pair Outputs Support Stacked DDR3 RDIMMs • CKE Powerdown Mode for Optimized System Power Consumption • 1.5V/1.35V/1.25V Phase Lock Loop Clock Driver for Buffering One Differential Clock Pair (CK and CK) and Distributing to Four Different

包装：散装 描述：TERM BLK 16P SIDE ENTRY 5MM PCB 连接器，互连器件 线对板

包装：散装 描述：TERM BLK 16P SIDE ENT 5.08MM PCB 连接器，互连器件 线对板

螺钉式接线端子

CRYSTAL 10.0000MHZ 12PF SMD

CRYSTAL 12.0000MHZ 12PF SMD

TERMINAL BLOCK

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