丝印代码：E11；Digital transistors (built-in resistors)

Features 1) The built-in bias resistor allows the configuration of an inverter circuit without connecting any external input resistors (see Equivalent circuit). 2) Each bias resistor is a thin-film resistor. Since they are completely insulated, the input can be positively biased. The insulat

Digital transistor(with built-in resistors)

罗姆开发了数字晶体管的标准产品。 •标准的数字晶体管;

丝印代码：E11；PNP -100mA -50V Digital Transistors (Bias Resistor Built-in Transistors)

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丝印代码：E11；PNP -100mA -50V Digital Transistor

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丝印代码：E11；PNP -100mA -50V Digital Transistors (Bias Resistor Built-in Transistors)

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丝印代码：E11；PNP -100mA -50V Digital Transistor (Bias Resistor Built-in Transistor)

Features 1) Built-In Biasing Resistors, 　　 R1 = 1kΩ, R2 = 10kΩ 2) Built-in bias resistors enable the configuration of 　an inverter circuit without connecting external 　input resistors (see inner circuit) . 3) Only the on/off conditions need to be set 　for operation, making the circuit desig

PNP -100mA -50V 数字晶体管(内置电阻器)

DTA113ZEB是一款电阻内置型晶体管。内置偏置电阻，因此输入侧无需外置电阻器也可构成逆变电路。

Digital transistor(with built-in resistors) (支持 AEC-Q101)

•标准的数字晶体管;

PNP -100mA -50V Digital Transistors (Bias Resistor Built-in Transistors)

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封装/外壳：SC-89，SOT-490 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：PNP -100MA -50V DIGITAL TRANSIST 分立半导体产品 晶体管 - 双极（BJT）- 单，预偏置

丝印代码：E11；PNP -100mA -50V Digital Transistor (Bias Resistor Built-in Transistor)

文件：1.05551 Mbytes Page：8 Pages

封装/外壳：SC-75，SOT-416 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：PNP DIGITAL TRANSISTOR (AEC-Q101 分立半导体产品 晶体管 - 双极（BJT）- 单，预偏置

PNP SILICON BIAS RESISTOR TRANSISTOR

This new series of digital transistors is designed to replace a single device and its external resistor bias network. The BRT (Bias Resistor Transistor) contains a single transistor with a monolithic bias network consisting of two resistors; a series base resistor and a base–emitter resistor. The

0.25關m Sea of Gates and Customer Structured Arrays

DESCRIPTION Oki’s 0.25µm Application-Specific Integrated Circuit (ASIC) products are available in both Sea Of Gates (SOG) and Customer Structured Array (CSA) architectures. Both the SOG-based MG115P series and the CSA-based MG75P series use a five-layer metal process on 0.25µm drawn (0.18µm L-eff

6-Pin DIP Optoisolators Darlington Output

6-Pin DIP Optoisolators Darlington Output The MTIL113 device consists of a gallium arsenide infrared emitting diode optically coupled to a monolithic silicon photodarlington detector. This device is designed for use in applications requiring high collector output currents at lower input currents

Reference Diode

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Reference Diode

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