DS90LV110T 1 to 10 LVDS Data/Clock Distributor

1FEATURES 2• Low jitter 800 Mbps fully differential data path • 145 ps (typ) of pk-pk jitter with PRBS = 223−1 data pattern at 800 Mbps • Single +3.3 V Supply • Less than 413 mW (typ) total power dissipation • Balanced output impedance • Output channel-to-channel skew is 35ps (typ) • Diffe

DS90LV110T 1 to 10 LVDS Data/Clock Distributor

1FEATURES 2• Low jitter 800 Mbps fully differential data path • 145 ps (typ) of pk-pk jitter with PRBS = 223−1 data pattern at 800 Mbps • Single +3.3 V Supply • Less than 413 mW (typ) total power dissipation • Balanced output impedance • Output channel-to-channel skew is 35ps (typ) • Diffe

1 to 10 LVDS Data/Clock Distributor

文件：1.09876 Mbytes Page：17 Pages

封装/外壳：28-TSSOP（0.173"，4.40mm 宽） 包装：卷带（TR） 描述：IC CLK BUF 1:10 400MHZ 28TSSOP 集成电路（IC） 时钟缓冲器，驱动器

DS90LV110AT 1 to 10 LVDS Data/Clock Distributor with Failsafe

1FEATURES 2• Low jitter 400 Mbps fully differential data path • 145 ps (typ) of pk-pk jitter with PRBS = 223−1 data pattern at 400 Mbps • Single +3.3 V Supply • Balanced output impedance • Output channel-to-channel skew is 35ps (typ) • Differential output voltage (VOD) is 320mV (typ) with

1 to 10 LVDS Data/Clock Distributor with Failsafe

文件：1.15191 Mbytes Page：17 Pages

1 to 10 LVDS Data/Clock Distributor with Failsafe

文件：391.81 Kbytes Page：9 Pages

1 to 10 LVDS Data/Clock Distributor with Failsafe

文件：1.2466 Mbytes Page：12 Pages

1 to 10 LVDS Data/Clock Distributor with Failsafe

文件：1.2584 Mbytes Page：12 Pages