丝印代码：DS90CR482VS；DS90CR481 / DS90CR482 48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz

1FEATURES 2• 3.168 Gbits/sec Bandwidth with 66 MHz Clock • 5.376 Gbits/sec Bandwidth with 112 MHz Clock • 65 - 112 MHz Input Clock Support • LVDS SER/DES Reduces Cable and Connector Size • Pre-Emphasis Reduces Cable Loading Effects • Optional DC Balance Encoding Reduces ISI Distortion • C

丝印代码：DS90CR482VS；DS90CR481 / DS90CR482 48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz

1FEATURES 2• 3.168 Gbits/sec Bandwidth with 66 MHz Clock • 5.376 Gbits/sec Bandwidth with 112 MHz Clock • 65 - 112 MHz Input Clock Support • LVDS SER/DES Reduces Cable and Connector Size • Pre-Emphasis Reduces Cable Loading Effects • Optional DC Balance Encoding Reduces ISI Distortion • C

丝印代码：DS90CR482VS；DS90CR481 / DS90CR482 48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz

1FEATURES 2• 3.168 Gbits/sec Bandwidth with 66 MHz Clock • 5.376 Gbits/sec Bandwidth with 112 MHz Clock • 65 - 112 MHz Input Clock Support • LVDS SER/DES Reduces Cable and Connector Size • Pre-Emphasis Reduces Cable Loading Effects • Optional DC Balance Encoding Reduces ISI Distortion • C

丝印代码：DS90CR482VS；DS90CR481 / DS90CR482 48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz

1FEATURES 2• 3.168 Gbits/sec Bandwidth with 66 MHz Clock • 5.376 Gbits/sec Bandwidth with 112 MHz Clock • 65 - 112 MHz Input Clock Support • LVDS SER/DES Reduces Cable and Connector Size • Pre-Emphasis Reduces Cable Loading Effects • Optional DC Balance Encoding Reduces ISI Distortion • C

丝印代码：DS90CR482VS；DS90CR481 / DS90CR482 48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz

1FEATURES 2• 3.168 Gbits/sec Bandwidth with 66 MHz Clock • 5.376 Gbits/sec Bandwidth with 112 MHz Clock • 65 - 112 MHz Input Clock Support • LVDS SER/DES Reduces Cable and Connector Size • Pre-Emphasis Reduces Cable Loading Effects • Optional DC Balance Encoding Reduces ISI Distortion • C

丝印代码：DS90CR482VS；DS90CR481 / DS90CR482 48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz

1FEATURES 2• 3.168 Gbits/sec Bandwidth with 66 MHz Clock • 5.376 Gbits/sec Bandwidth with 112 MHz Clock • 65 - 112 MHz Input Clock Support • LVDS SER/DES Reduces Cable and Connector Size • Pre-Emphasis Reduces Cable Loading Effects • Optional DC Balance Encoding Reduces ISI Distortion • C

丝印代码：DS90CR482VS；DS90CR481 / DS90CR482 48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz

1FEATURES 2• 3.168 Gbits/sec Bandwidth with 66 MHz Clock • 5.376 Gbits/sec Bandwidth with 112 MHz Clock • 65 - 112 MHz Input Clock Support • LVDS SER/DES Reduces Cable and Connector Size • Pre-Emphasis Reduces Cable Loading Effects • Optional DC Balance Encoding Reduces ISI Distortion • C

丝印代码：DS90CR482VS；DS90CR481 / DS90CR482 48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz

1FEATURES 2• 3.168 Gbits/sec Bandwidth with 66 MHz Clock • 5.376 Gbits/sec Bandwidth with 112 MHz Clock • 65 - 112 MHz Input Clock Support • LVDS SER/DES Reduces Cable and Connector Size • Pre-Emphasis Reduces Cable Loading Effects • Optional DC Balance Encoding Reduces ISI Distortion • C

丝印代码：DS90CR482VS；DS90CR481 / DS90CR482 48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz

1FEATURES 2• 3.168 Gbits/sec Bandwidth with 66 MHz Clock • 5.376 Gbits/sec Bandwidth with 112 MHz Clock • 65 - 112 MHz Input Clock Support • LVDS SER/DES Reduces Cable and Connector Size • Pre-Emphasis Reduces Cable Loading Effects • Optional DC Balance Encoding Reduces ISI Distortion • C

丝印代码：DS90CR482VS；DS90CR481 / DS90CR482 48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz

1FEATURES 2• 3.168 Gbits/sec Bandwidth with 66 MHz Clock • 5.376 Gbits/sec Bandwidth with 112 MHz Clock • 65 - 112 MHz Input Clock Support • LVDS SER/DES Reduces Cable and Connector Size • Pre-Emphasis Reduces Cable Loading Effects • Optional DC Balance Encoding Reduces ISI Distortion • C

丝印代码：DS90CR482VS；DS90CR481 / DS90CR482 48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz

1FEATURES 2• 3.168 Gbits/sec Bandwidth with 66 MHz Clock • 5.376 Gbits/sec Bandwidth with 112 MHz Clock • 65 - 112 MHz Input Clock Support • LVDS SER/DES Reduces Cable and Connector Size • Pre-Emphasis Reduces Cable Loading Effects • Optional DC Balance Encoding Reduces ISI Distortion • C

48-Bit LVDS Channel Link SER/DES ??65 - 112 MHz

文件：1.6522 Mbytes Page：25 Pages

封装/外壳：100-TQFP 功能：解串器 包装：卷带（TR） 描述：IC SERIALIZER 48BIT 100-TQFP 集成电路（IC） 串行器，解串器

48-Bit LVDS Channel Link SER/DES ??65 - 112 MHz

文件：1.6522 Mbytes Page：25 Pages

48-Bit LVDS Channel Link SER/DES ??65 - 112 MHz

文件：1.6522 Mbytes Page：25 Pages

48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz

文件：899.87 Kbytes Page：21 Pages

48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz

文件：904.79 Kbytes Page：21 Pages

48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz

文件：904.79 Kbytes Page：21 Pages

48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz

文件：899.87 Kbytes Page：21 Pages