位置：首页 > IC中文资料第1723页 > DS90CR482VSX
| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
丝印代码：DS90CR482VS；DS90CR481 / DS90CR482 48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz 1FEATURES 2• 3.168 Gbits/sec Bandwidth with 66 MHz Clock • 5.376 Gbits/sec Bandwidth with 112 MHz Clock • 65 - 112 MHz Input Clock Support • LVDS SER/DES Reduces Cable and Connector Size • Pre-Emphasis Reduces Cable Loading Effects • Optional DC Balance Encoding Reduces ISI Distortion • C | TI 德州仪器 |   | ||
丝印代码：DS90CR482VS；DS90CR481 / DS90CR482 48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz 1FEATURES 2• 3.168 Gbits/sec Bandwidth with 66 MHz Clock • 5.376 Gbits/sec Bandwidth with 112 MHz Clock • 65 - 112 MHz Input Clock Support • LVDS SER/DES Reduces Cable and Connector Size • Pre-Emphasis Reduces Cable Loading Effects • Optional DC Balance Encoding Reduces ISI Distortion • C | TI 德州仪器 | | ||
丝印代码：DS90CR482VS；DS90CR481 / DS90CR482 48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz 1FEATURES 2• 3.168 Gbits/sec Bandwidth with 66 MHz Clock • 5.376 Gbits/sec Bandwidth with 112 MHz Clock • 65 - 112 MHz Input Clock Support • LVDS SER/DES Reduces Cable and Connector Size • Pre-Emphasis Reduces Cable Loading Effects • Optional DC Balance Encoding Reduces ISI Distortion • C | TI 德州仪器 | | ||
丝印代码：DS90CR482VS；DS90CR481 / DS90CR482 48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz 1FEATURES 2• 3.168 Gbits/sec Bandwidth with 66 MHz Clock • 5.376 Gbits/sec Bandwidth with 112 MHz Clock • 65 - 112 MHz Input Clock Support • LVDS SER/DES Reduces Cable and Connector Size • Pre-Emphasis Reduces Cable Loading Effects • Optional DC Balance Encoding Reduces ISI Distortion • C | TI 德州仪器 | | ||
丝印代码：DS90CR482VS；DS90CR481 / DS90CR482 48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz 1FEATURES 2• 3.168 Gbits/sec Bandwidth with 66 MHz Clock • 5.376 Gbits/sec Bandwidth with 112 MHz Clock • 65 - 112 MHz Input Clock Support • LVDS SER/DES Reduces Cable and Connector Size • Pre-Emphasis Reduces Cable Loading Effects • Optional DC Balance Encoding Reduces ISI Distortion • C | TI 德州仪器 | | ||
丝印代码：DS90CR482VS；DS90CR481 / DS90CR482 48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz 1FEATURES 2• 3.168 Gbits/sec Bandwidth with 66 MHz Clock • 5.376 Gbits/sec Bandwidth with 112 MHz Clock • 65 - 112 MHz Input Clock Support • LVDS SER/DES Reduces Cable and Connector Size • Pre-Emphasis Reduces Cable Loading Effects • Optional DC Balance Encoding Reduces ISI Distortion • C | TI 德州仪器 | | ||
丝印代码：DS90CR482VS；DS90CR481 / DS90CR482 48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz 1FEATURES 2• 3.168 Gbits/sec Bandwidth with 66 MHz Clock • 5.376 Gbits/sec Bandwidth with 112 MHz Clock • 65 - 112 MHz Input Clock Support • LVDS SER/DES Reduces Cable and Connector Size • Pre-Emphasis Reduces Cable Loading Effects • Optional DC Balance Encoding Reduces ISI Distortion • C | TI 德州仪器 | | ||
丝印代码：DS90CR482VS；DS90CR481 / DS90CR482 48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz 1FEATURES 2• 3.168 Gbits/sec Bandwidth with 66 MHz Clock • 5.376 Gbits/sec Bandwidth with 112 MHz Clock • 65 - 112 MHz Input Clock Support • LVDS SER/DES Reduces Cable and Connector Size • Pre-Emphasis Reduces Cable Loading Effects • Optional DC Balance Encoding Reduces ISI Distortion • C | TI 德州仪器 | | ||
丝印代码：DS90CR482VS；DS90CR481 / DS90CR482 48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz 1FEATURES 2• 3.168 Gbits/sec Bandwidth with 66 MHz Clock • 5.376 Gbits/sec Bandwidth with 112 MHz Clock • 65 - 112 MHz Input Clock Support • LVDS SER/DES Reduces Cable and Connector Size • Pre-Emphasis Reduces Cable Loading Effects • Optional DC Balance Encoding Reduces ISI Distortion • C | TI 德州仪器 | | ||
丝印代码：DS90CR482VS；DS90CR481 / DS90CR482 48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz 1FEATURES 2• 3.168 Gbits/sec Bandwidth with 66 MHz Clock • 5.376 Gbits/sec Bandwidth with 112 MHz Clock • 65 - 112 MHz Input Clock Support • LVDS SER/DES Reduces Cable and Connector Size • Pre-Emphasis Reduces Cable Loading Effects • Optional DC Balance Encoding Reduces ISI Distortion • C | TI 德州仪器 | | ||
丝印代码：DS90CR482VS；DS90CR481 / DS90CR482 48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz 1FEATURES 2• 3.168 Gbits/sec Bandwidth with 66 MHz Clock • 5.376 Gbits/sec Bandwidth with 112 MHz Clock • 65 - 112 MHz Input Clock Support • LVDS SER/DES Reduces Cable and Connector Size • Pre-Emphasis Reduces Cable Loading Effects • Optional DC Balance Encoding Reduces ISI Distortion • C | TI 德州仪器 | | ||
48-Bit LVDS Channel Link SER/DES ??65 - 112 MHz 文件：1.6522 Mbytes Page：25 Pages | TI 德州仪器 | | ||
封装/外壳：100-TQFP 功能：解串器 包装：卷带（TR） 描述：IC SERIALIZER 48BIT 100-TQFP 集成电路（IC） 串行器，解串器 | TI 德州仪器 | | ||
48-Bit LVDS Channel Link SER/DES ??65 - 112 MHz 文件：1.6522 Mbytes Page：25 Pages | TI 德州仪器 | | ||
48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz 文件：904.79 Kbytes Page：21 Pages | NSC 国半 | | ||
48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz 文件：899.87 Kbytes Page：21 Pages | NSC 国半 | | ||
48-Bit LVDS Channel Link SER/DES ??65 - 112 MHz 文件：1.6522 Mbytes Page：25 Pages | TI 德州仪器 | | ||
48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz 文件：904.79 Kbytes Page：21 Pages | NSC 国半 | | ||
48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz 文件：899.87 Kbytes Page：21 Pages | NSC 国半 | |
DS90CR482VSX产品属性
- 类型
描述
- 型号
DS90CR482VSX
- 功能描述
LVDS 接口集成电路
- RoHS
否
- 制造商
Texas Instruments
- 激励器数量
4
- 接收机数量
4
- 数据速率
155.5 Mbps
- 工作电源电压
5 V
- 最大功率耗散
1025 mW
- 最大工作温度
+ 85 C
- 封装/箱体
SOIC-16 Narrow
- 封装
Reel
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
TI |
25+ |
TQFP-100(14x14) |
7734 |
样件支持,可原厂排单订货! |
|||
TI |
25+ |
TQFP-100(14x14) |
7786 |
正规渠道,免费送样。支持账期,BOM一站式配齐 |
|||
TI/德州仪器 |
2026+ |
100-TQFP |
65248 |
百分百原装现货 实单必成 |
|||
TI(德州仪器) |
2021+ |
TQFP-100(14x14) |
499 |
||||
DALLAS |
16+ |
QFP |
4000 |
进口原装现货/价格优势! |
|||
TI |
22+ |
100TQFP |
9000 |
原厂渠道,现货配单 |
|||
NSC |
23+ |
BGAQFP |
8659 |
原装公司现货!原装正品价格优势. |
|||
NationalSemiconductor |
25+23+ |
100-TQFP |
19435 |
绝对原装正品全新进口深圳现货 |
|||
Texas Instruments |
24+25+ |
16500 |
全新原厂原装现货!受权代理!可送样可提供技术支持! |
||||
NSC |
23+ |
100-TQFP |
65480 |
DS90CR482VSX芯片相关品牌
DS90CR482VSX规格书下载地址
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