DS90CR481 / DS90CR482 48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz

1FEATURES 2• 3.168 Gbits/sec Bandwidth with 66 MHz Clock • 5.376 Gbits/sec Bandwidth with 112 MHz Clock • 65 - 112 MHz Input Clock Support • LVDS SER/DES Reduces Cable and Connector Size • Pre-Emphasis Reduces Cable Loading Effects • Optional DC Balance Encoding Reduces ISI Distortion • C

DS90CR481 / DS90CR482 48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz

1FEATURES 2• 3.168 Gbits/sec Bandwidth with 66 MHz Clock • 5.376 Gbits/sec Bandwidth with 112 MHz Clock • 65 - 112 MHz Input Clock Support • LVDS SER/DES Reduces Cable and Connector Size • Pre-Emphasis Reduces Cable Loading Effects • Optional DC Balance Encoding Reduces ISI Distortion • C

48 位 LVDS 频道链接串行器 - 65 - 112MHz

The DS90CR481 transmitter converts 48 bits of CMOS/TTL data into eight LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a ninth LVDS link. Every cycle of the transmit clock 48 bits of input data are sampled an • 3.168 Gbits/sec Bandwidth with 66 MHz Clock\n• 5.376 Gbits/sec Bandwidth with 112 MHz Clock\n• 65 - 112 MHz Input Clock Support \n• LVDS SER/DES Reduces Cable and Connector Size\n• Pre-Emphasis Reduces Cable Loading Effects\n• Optional DC Balance Encoding Reduces ISI Distortion\n• Cable Deskew of ;

48-Bit LVDS Channel Link SER/DES ??65 - 112 MHz

文件：1.6522 Mbytes Page：25 Pages

48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz

文件：899.87 Kbytes Page：21 Pages

48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz

文件：904.79 Kbytes Page：21 Pages

丝印代码：DS90CR481VJD；DS90CR481 / DS90CR482 48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz

1FEATURES 2• 3.168 Gbits/sec Bandwidth with 66 MHz Clock • 5.376 Gbits/sec Bandwidth with 112 MHz Clock • 65 - 112 MHz Input Clock Support • LVDS SER/DES Reduces Cable and Connector Size • Pre-Emphasis Reduces Cable Loading Effects • Optional DC Balance Encoding Reduces ISI Distortion • C

丝印代码：DS90CR481VJD；DS90CR481 / DS90CR482 48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz

1FEATURES 2• 3.168 Gbits/sec Bandwidth with 66 MHz Clock • 5.376 Gbits/sec Bandwidth with 112 MHz Clock • 65 - 112 MHz Input Clock Support • LVDS SER/DES Reduces Cable and Connector Size • Pre-Emphasis Reduces Cable Loading Effects • Optional DC Balance Encoding Reduces ISI Distortion • C

丝印代码：DS90CR481VJD；DS90CR481 / DS90CR482 48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz

1FEATURES 2• 3.168 Gbits/sec Bandwidth with 66 MHz Clock • 5.376 Gbits/sec Bandwidth with 112 MHz Clock • 65 - 112 MHz Input Clock Support • LVDS SER/DES Reduces Cable and Connector Size • Pre-Emphasis Reduces Cable Loading Effects • Optional DC Balance Encoding Reduces ISI Distortion • C

丝印代码：DS90CR481VJD；DS90CR481 / DS90CR482 48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz

1FEATURES 2• 3.168 Gbits/sec Bandwidth with 66 MHz Clock • 5.376 Gbits/sec Bandwidth with 112 MHz Clock • 65 - 112 MHz Input Clock Support • LVDS SER/DES Reduces Cable and Connector Size • Pre-Emphasis Reduces Cable Loading Effects • Optional DC Balance Encoding Reduces ISI Distortion • C

丝印代码：DS90CR481VJD；DS90CR481 / DS90CR482 48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz

1FEATURES 2• 3.168 Gbits/sec Bandwidth with 66 MHz Clock • 5.376 Gbits/sec Bandwidth with 112 MHz Clock • 65 - 112 MHz Input Clock Support • LVDS SER/DES Reduces Cable and Connector Size • Pre-Emphasis Reduces Cable Loading Effects • Optional DC Balance Encoding Reduces ISI Distortion • C

丝印代码：DS90CR481VJD；DS90CR481 / DS90CR482 48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz

1FEATURES 2• 3.168 Gbits/sec Bandwidth with 66 MHz Clock • 5.376 Gbits/sec Bandwidth with 112 MHz Clock • 65 - 112 MHz Input Clock Support • LVDS SER/DES Reduces Cable and Connector Size • Pre-Emphasis Reduces Cable Loading Effects • Optional DC Balance Encoding Reduces ISI Distortion • C

丝印代码：DS90CR481VJD；DS90CR481 / DS90CR482 48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz

1FEATURES 2• 3.168 Gbits/sec Bandwidth with 66 MHz Clock • 5.376 Gbits/sec Bandwidth with 112 MHz Clock • 65 - 112 MHz Input Clock Support • LVDS SER/DES Reduces Cable and Connector Size • Pre-Emphasis Reduces Cable Loading Effects • Optional DC Balance Encoding Reduces ISI Distortion • C

丝印代码：DS90CR481VJD；DS90CR481 / DS90CR482 48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz

1FEATURES 2• 3.168 Gbits/sec Bandwidth with 66 MHz Clock • 5.376 Gbits/sec Bandwidth with 112 MHz Clock • 65 - 112 MHz Input Clock Support • LVDS SER/DES Reduces Cable and Connector Size • Pre-Emphasis Reduces Cable Loading Effects • Optional DC Balance Encoding Reduces ISI Distortion • C

DS90CR481 / DS90CR482 48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz

1FEATURES 2• 3.168 Gbits/sec Bandwidth with 66 MHz Clock • 5.376 Gbits/sec Bandwidth with 112 MHz Clock • 65 - 112 MHz Input Clock Support • LVDS SER/DES Reduces Cable and Connector Size • Pre-Emphasis Reduces Cable Loading Effects • Optional DC Balance Encoding Reduces ISI Distortion • C

48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz

文件：899.87 Kbytes Page：21 Pages

48-Bit LVDS Channel Link SER/DES ??65 - 112 MHz

文件：1.6522 Mbytes Page：25 Pages

48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz

文件：904.79 Kbytes Page：21 Pages

48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz

文件：899.87 Kbytes Page：21 Pages

封装/外壳：100-TQFP 功能：串行器 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC SERIALIZER 48BIT 100-TQFP 集成电路（IC） 串行器，解串器

48-Bit LVDS Channel Link SER/DES ??65 - 112 MHz

文件：1.6522 Mbytes Page：25 Pages

48-Bit LVDS Channel Link SER/DES ??65 - 112 MHz

文件：1.6522 Mbytes Page：25 Pages