Quad Unified Bus Transceiver

General Description\nThe DS8641 is a quad high speed drivers/receivers designed for use in bus organized data transmission systems interconnected by terminated 120Ω impedance lines. The external termination is intended to be a 180Ω resistor from the bus to the +5V logic supply together with a 390Ω r ■ 4 separate driver/receiver pairs per package\n■ Guaranteed minimum bus noise immunity of 0.6V, 1.1V typ\n■ Temperature insensitive receiver thresholds track bus logic levels\n■ 30 µA typical bus terminal current with normal VCC or with VCC = 0V\n■ Open collector driver output allows wire-OR connec;

Quad Unified Bus Transceiver

文件：78.13 Kbytes Page：5 Pages

Quad Unified Bus Transceiver

文件：78.13 Kbytes Page：5 Pages

Low Power, Rail-to-Rail Output Precision JFET Amplifier

GENERAL DESCRIPTION The AD8641/AD8642/AD8643 are low power, precision JFET input amplifiers featuring extremely low input bias current and rail-to-rail output. The ability to swing nearly rail-to-rail at the input and rail-to-rail at the output enables designers to buffer CMOS DACs, ASICs, and ot

Low Power, Rail-to-Rail Output Precision JFET Amplifier

GENERAL DESCRIPTION The AD8641/AD8642/AD8643 are low power, precision JFET input amplifiers featuring extremely low input bias current and rail-to-rail output. The ability to swing nearly rail-to-rail at the input and rail-to-rail at the output enables designers to buffer CMOS DACs, ASICs, and ot

Low Power, Rail-to-Rail Output Precision JFET Amplifier

GENERAL DESCRIPTION The AD8641/AD8642/AD8643 are low power, precision JFET input amplifiers featuring extremely low input bias current and rail-to-rail output. The ability to swing nearly rail-to-rail at the input and rail-to-rail at the output enables designers to buffer CMOS DACs, ASICs, and ot