丝印代码：DS34C86TM；DS34C86T Quad CMOS Differential Line Receiver

1FEATURES 2• CMOS Design for Low Power • ±0.2V Sensitivity Over the Input Common Mode Voltage Range • Typical Propagation Delays: 19 ns • Typical Input Hysteresis: 60 mV • Inputs Won't Load Line when VCC = 0V • Meets the Requirements of EIA Standard RS- 422 • TRI-STATE Outputs for System

丝印代码：DS34C86TM；DS34C86T Quad CMOS Differential Line Receiver

1FEATURES 2• CMOS Design for Low Power • ±0.2V Sensitivity Over the Input Common Mode Voltage Range • Typical Propagation Delays: 19 ns • Typical Input Hysteresis: 60 mV • Inputs Won't Load Line when VCC = 0V • Meets the Requirements of EIA Standard RS- 422 • TRI-STATE Outputs for System

丝印代码：DS34C86TM；DS34C86T Quad CMOS Differential Line Receiver

1FEATURES 2• CMOS Design for Low Power • ±0.2V Sensitivity Over the Input Common Mode Voltage Range • Typical Propagation Delays: 19 ns • Typical Input Hysteresis: 60 mV • Inputs Won't Load Line when VCC = 0V • Meets the Requirements of EIA Standard RS- 422 • TRI-STATE Outputs for System

丝印代码：DS34C86TM；DS34C86T Quad CMOS Differential Line Receiver

1FEATURES 2• CMOS Design for Low Power • ±0.2V Sensitivity Over the Input Common Mode Voltage Range • Typical Propagation Delays: 19 ns • Typical Input Hysteresis: 60 mV • Inputs Won't Load Line when VCC = 0V • Meets the Requirements of EIA Standard RS- 422 • TRI-STATE Outputs for System

丝印代码：DS34C86TM；DS34C86T Quad CMOS Differential Line Receiver

1FEATURES 2• CMOS Design for Low Power • ±0.2V Sensitivity Over the Input Common Mode Voltage Range • Typical Propagation Delays: 19 ns • Typical Input Hysteresis: 60 mV • Inputs Won't Load Line when VCC = 0V • Meets the Requirements of EIA Standard RS- 422 • TRI-STATE Outputs for System

丝印代码：DS34C86TM；DS34C86T Quad CMOS Differential Line Receiver

1FEATURES 2• CMOS Design for Low Power • ±0.2V Sensitivity Over the Input Common Mode Voltage Range • Typical Propagation Delays: 19 ns • Typical Input Hysteresis: 60 mV • Inputs Won't Load Line when VCC = 0V • Meets the Requirements of EIA Standard RS- 422 • TRI-STATE Outputs for System

丝印代码：DS34C86TM；DS34C86T Quad CMOS Differential Line Receiver

1FEATURES 2• CMOS Design for Low Power • ±0.2V Sensitivity Over the Input Common Mode Voltage Range • Typical Propagation Delays: 19 ns • Typical Input Hysteresis: 60 mV • Inputs Won't Load Line when VCC = 0V • Meets the Requirements of EIA Standard RS- 422 • TRI-STATE Outputs for System

丝印代码：DS34C86TM；DS34C86T Quad CMOS Differential Line Receiver

1FEATURES 2• CMOS Design for Low Power • ±0.2V Sensitivity Over the Input Common Mode Voltage Range • Typical Propagation Delays: 19 ns • Typical Input Hysteresis: 60 mV • Inputs Won't Load Line when VCC = 0V • Meets the Requirements of EIA Standard RS- 422 • TRI-STATE Outputs for System

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 包装：卷带（TR） 描述：IC RECEIVER 0/4 16SOIC 集成电路（IC） 驱动器，接收器，收发器

Quad CMOS Differential Line Receiver

文件：196.06 Kbytes Page：8 Pages

DS34C86T Quad CMOS Differential Line Receiver

文件：839.36 Kbytes Page：13 Pages

DS34C86T Quad CMOS Differential Line Receiver

文件：839.36 Kbytes Page：13 Pages

DS34C86T Quad CMOS Differential Line Receiver

文件：839.36 Kbytes Page：13 Pages

DS34C86T Quad CMOS Differential Line Receiver

文件：839.36 Kbytes Page：13 Pages

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 包装：卷带（TR） 描述：IC RECEIVER 0/4 16SOIC 集成电路（IC） 驱动器，接收器，收发器

DS34C86T Quad CMOS Differential Line Receiver

文件：839.36 Kbytes Page：13 Pages

DS34C86T Quad CMOS Differential Line Receiver

文件：839.36 Kbytes Page：13 Pages

Quad CMOS Differential Line Receiver

文件：196.06 Kbytes Page：8 Pages

CMOS QUAD 3-STATE DIFFERENTIAL LINE RECEIVER

DESCRIPTION The ST34C86 is a quad differential line receiver designed to meet the RS-422, RS-423, and Federal Standard 1020 and 1030 for balanced and unbalanced digital data transmission, while retaining the low power characteristics of CMOS. The ST34C86 has an input sensivity of 200mV over the c

CMOS QUAD 3-STATE DIFFERENTIAL LINE RECEIVER

DESCRIPTION The ST34C86 is a quad differential line receiver designed to meet the RS-422, RS-423, and Federal Standard 1020 and 1030 for balanced and unbalanced digital data transmission, while retaining the low power characteristics of CMOS. The ST34C86 has an input sensivity of 200mV over the c

CMOS QUAD 3-STATE DIFFERENTIAL LINE RECEIVER

DESCRIPTION The ST34C86 is a quad differential line receiver designed to meet the RS-422, RS-423, and Federal Standard 1020 and 1030 for balanced and unbalanced digital data transmission, while retaining the low power characteristics of CMOS. The ST34C86 has an input sensivity of 200mV over the c