具有 DDR LVDS 并行接口的 125MHz 至 312.5MHz FPGA-Link 解串器

The DS32EL0124/DS32ELX0124 integrates clock and data recovery modules for high-speed serial communication over FR-4 printed circuit board backplanes, balanced cables, and optical fiber. This easy-to-use chipset integrates advanced signal and clock conditioning functions, with an FPGA friendly interf • 5-bit DDR LVDS Parallel Data Interface\n• Selectable DC-Balance Decoder\n• Remote Sense for Automatic Detection and Negotiation of Link Status\n• LVDS Parallel Interface\n• Supports Output Data-Valid Signaling\n• On Chip LC VCOs\n• Retimed Serial Output (ELX device only)\n• Configurable via SMBus\;

DS32EL0124 , DS32ELX0124 125 MHz - 312.5 MHz FPGA-Link Deserializer with DDR LVDS Parallel Interface

文件：2.61644 Mbytes Page：34 Pages

125 MHz - 312.5 MHz Deserializer with DDR LVDS Parallel Interface

文件：459.15 Kbytes Page：24 Pages

125 MHz . 312.5 MHz Deserializer with DDR LVDS Parallel Interface

文件：490.62 Kbytes Page：26 Pages

125 MHz- 312.5 MHz FPGA-Link Deserializer with DDR LVDS Parallel Interface

文件：1.58599 Mbytes Page：28 Pages

125 MHz- 312.5 MHz FPGA-Link Deserializer with DDR LVDS Parallel Interface

文件：1.58599 Mbytes Page：28 Pages

封装/外壳：48-WFQFN 裸露焊盘 功能：解串器 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC DESERIAL W/DDR LVDS 48WQFN 集成电路（IC） 串行器，解串器

125 MHz- 312.5 MHz FPGA-Link Deserializer with DDR LVDS Parallel Interface

文件：1.58599 Mbytes Page：28 Pages

DS32EL0124 , DS32ELX0124 125 MHz - 312.5 MHz FPGA-Link Deserializer with DDR LVDS Parallel Interface

文件：2.61644 Mbytes Page：34 Pages

DS32EL0124 , DS32ELX0124 125 MHz - 312.5 MHz FPGA-Link Deserializer with DDR LVDS Parallel Interface

文件：2.61644 Mbytes Page：34 Pages

125 MHz- 312.5 MHz FPGA-Link Deserializer with DDR LVDS Parallel Interface

文件：1.58599 Mbytes Page：28 Pages

DS32EL0124 , DS32ELX0124 125 MHz - 312.5 MHz FPGA-Link Deserializer with DDR LVDS Parallel Interface

文件：2.61644 Mbytes Page：34 Pages

封装/外壳：48-WFQFN 裸露焊盘 功能：解串器 包装：卷带（TR） 描述：IC DESERIAL W/DDR LVDS 48WQFN 集成电路（IC） 串行器，解串器

DS32EL0124 , DS32ELX0124 125 MHz - 312.5 MHz FPGA-Link Deserializer with DDR LVDS Parallel Interface

文件：2.61644 Mbytes Page：34 Pages