SBR 肖特基二极管

丝印代码：DS280DF8；DS280DF810 28 Gbps Multi-Rate 8-Channel Retimer

文件：2.08759 Mbytes Page：51 Pages

丝印代码：DS280DF8；DS280DF810 28 Gbps Multi-Rate 8-Channel Retimer

文件：2.08759 Mbytes Page：51 Pages

丝印代码：DS280DF8W；DS280DF810 28 Gbps Multi-Rate 8-Channel Retimer

文件：2.08759 Mbytes Page：51 Pages

丝印代码：DS280DF8W；DS280DF810 28 Gbps Multi-Rate 8-Channel Retimer

文件：2.08759 Mbytes Page：51 Pages

28Gbps 低功耗 8 通道转接驱动器

DS280BR820 是一款超低功耗、高性能八通道线性均衡器，支持数据传输速率高达 28Gbps 的多速率、多协议接口。该器件可用于扩展长度范围并提高背板、前端口和芯片至芯片应用的高速串行链路的稳定性。 应用。\n\nDS280BR820 均衡器的线性特质保留了发射信号的特性，因此允许主机与链路合作伙伴 ASIC 自由协商发射均衡器系数 (100G-CR4/KR4)。这种链路协商协议的透明管理有助于在对延迟影响最小的情况下实现系统级互操作性。每条通道独立运行，允许 DS280BR820 进行独立信道前向纠错 (FEC)。\n\nDS280BR820 将小型封装尺寸、经优化的高速信号退出和引脚兼 • 八通道多协议线性均衡器，可支持传输速率高达 28Gbps 的接口 \n• 低功耗：93mW/通道（典型值） \n• 无需散热器\n• 无缝支持链路协商、自动协商和前向纠错 (FEC) 直通功能的直线均衡\n• 扩展通道长度，超出正常专用集成电路 (ASIC) 到 ASIC 性能 17dB+\n• 超低延迟：100ps（典型值）\n• 低附加随机抖动\n• 采用集成 Rx 和 Tx 交流耦合电容的小型 8mm x 13mm 小型球状引脚栅格阵列 (BGA) 封装，可实现简易直通路由 \n• 独特的引脚分配支持在封装下对高速信号进行路由 \n• 提供引脚兼容的重定时器 \n• 2.5V±5&#;

28Gbps 多速率 8 通道重定时器

DS280DF810 是一款具有集成信号调节功能的八通道多速率重定时器。该器件用于扩展有损且存在串扰的远距离高速串行链路的延伸长度并提升稳定性，同时实现不高于 10-15 的比特误码率 (BER)。\n\nDS280DF810 各通道的串行数据速率均可独立锁定在 20.2Gbps 至 28.4Gbps 的连续范围内或者支持的任意子速率（速率的一半和四分之一），包括 10.1376Gbps、10.3125Gbps 和 12.5Gbps 等关键数据速率，因此该器件支持独立通道前向纠错 (FEC) 直通。\n\n印刷电路板 (PCB) 上集成了物理交流耦合电容（TX 与 RX），无需使用外部电容。D • 具有集成信号调节功能的八通道多速率重定时器\n• 所有通道均可独立锁定在 20.2Gbps 至 28.4Gbps 的范围内（包括 10.1376Gbps、10.3125Gbps、12.5Gbps 等子速率）\n• 超低延迟：28.4Gbps 数据速率下的典型延迟;

Low Differential Pressure Gases

Description: The Magnehelic® gauge uses magnetic coupling from the movement of a silicon rubber diaphragm onto a helical pointer drive shaft. This measurement is friction free, accurate at very low differential pressures, and resistant to shock and vibration. The standard aluminum housing can be

Differential Pressure Gauge with Alarms

Description: Based on the Magnehelic® design, this gauge retains the low DP sensitivity and accuracy whilst adding two relay outputs for high and low DP alarms. The Photohelic® principle uses the standard gauge pointer to interrupt infra-red beams at the adjustable set points, which then drive th

Differential Pressure Gauge with Transmitter

Description: The standard, easy to read Magnehelic® dial gauge gives local indication of very low differential pressures in air or gas applications. Additionally, a two-wire 4-20mA transmission is provided from a built in strain gauge DP monitor, allowing remote monitoring or control. Span and ze

1-Wire Digital Potentiometer

FEATURES ● Single element 256-position linear taper potentiometer ● Supports potentiometer terminal working voltages up to 11V ● Potentiometer terminal voltage independent of supply voltage ● Potentiometer wiper position controlled and read over minimal 1-Wire bus interface ● 100 kΩ

1-Wire Digital Potentiometer

FEATURES ● Single element 256-position linear taper potentiometer ● Supports potentiometer terminal working voltages up to 11V ● Potentiometer terminal voltage independent of supply voltage ● Potentiometer wiper position controlled and read over minimal 1-Wire bus interface ● 100 kΩ

1-Wire Digital Potentiometer

FEATURES ● Single element 256-position linear taper potentiometer ● Supports potentiometer terminal working voltages up to 11V ● Potentiometer terminal voltage independent of supply voltage ● Potentiometer wiper position controlled and read over minimal 1-Wire bus interface ● 100 kΩ

1-Wire Digital Potentiometer

FEATURES ● Single element 256-position linear taper potentiometer ● Supports potentiometer terminal working voltages up to 11V ● Potentiometer terminal voltage independent of supply voltage ● Potentiometer wiper position controlled and read over minimal 1-Wire bus interface ● 100 kΩ

1-Wire Digital Potentiometer

FEATURES ● Single element 256-position linear taper potentiometer ● Supports potentiometer terminal working voltages up to 11V ● Potentiometer terminal voltage independent of supply voltage ● Potentiometer wiper position controlled and read over minimal 1-Wire bus interface ● 100 kΩ

1-Wire Digital Potentiometer

FEATURES ● Single element 256-position linear taper potentiometer ● Supports potentiometer terminal working voltages up to 11V ● Potentiometer terminal voltage independent of supply voltage ● Potentiometer wiper position controlled and read over minimal 1-Wire bus interface ● 100 kΩ

1-Wire Digital Potentiometer

FEATURES ● Single element 256-position linear taper potentiometer ● Supports potentiometer terminal working voltages up to 11V ● Potentiometer terminal voltage independent of supply voltage ● Potentiometer wiper position controlled and read over minimal 1-Wire bus interface ● 100 kΩ

1-Wire Digital Potentiometer

FEATURES ● Single element 256-position linear taper potentiometer ● Supports potentiometer terminal working voltages up to 11V ● Potentiometer terminal voltage independent of supply voltage ● Potentiometer wiper position controlled and read over minimal 1-Wire bus interface ● 100 kΩ

1-Wire Digital Potentiometer

FEATURES ● Single element 256-position linear taper potentiometer ● Supports potentiometer terminal working voltages up to 11V ● Potentiometer terminal voltage independent of supply voltage ● Potentiometer wiper position controlled and read over minimal 1-Wire bus interface ● 100 kΩ

1-Wire Digital Potentiometer

FEATURES ● Single element 256-position linear taper potentiometer ● Supports potentiometer terminal working voltages up to 11V ● Potentiometer terminal voltage independent of supply voltage ● Potentiometer wiper position controlled and read over minimal 1-Wire bus interface ● 100 kΩ

I2C Low-Voltage SHA-3 Authenticator

Benefits and Features ● Robust Countermeasures Protect Against Security Attacks • All Stored Data Cryptographically Protected from Discovery ● Efficient Secure Hash Algorithm to Authenticate Peripherals • FIPS 202-Compliant SHA-3 Algorithm for Challenge/Response Authentication • FIPS 198-

I2C Low-Voltage SHA-3 Authenticator

Benefits and Features ● Robust Countermeasures Protect Against Security Attacks • All Stored Data Cryptographically Protected from Discovery ● Efficient Secure Hash Algorithm to Authenticate Peripherals • FIPS 202-Compliant SHA-3 Algorithm for Challenge/Response Authentication • FIPS 198-

DeepCover Secure Authenticator

Benefits and Features ● ECC-256 Compute Engine • FIPS 186 ECDSA P256 Signature and Verification • ECDH Key Exchange with Authentication Prevents Man-in-the-Middle Attacks • ECDSA Authenticated R/W of Configurable Memory ● FIPS 180 SHA-256 Compute Engine • HMAC ● SHA-256 OTP (One-Time Pad)

DeepCover Secure ECDSA Bidirectional Authenticator with ChipDNA PUF Protection

Benefits and Features ● Robust Countermeasures Protect Against Security Attacks • Patented Physically Unclonable Function Secures Device Data • Actively Monitored Die Shield Detects and Reacts to Intrusion Attempts • All Stored Data Cryptographically Protected from Discovery ● ECDSA Authe

DeepCover Secure ECDSA Bidirectional Authenticator with ChipDNA PUF Protection

Benefits and Features ● Robust Countermeasures Protect Against Security Attacks • Patented Physically Unclonable Function Secures Device Data • Actively Monitored Die Shield Detects and Reacts to Intrusion Attempts • All Stored Data Cryptographically Protected from Discovery ● ECDSA Authe

1Kb Protected 1-Wire EEPROM with SHA-1 Engine

Features ● 1024 Bits of EEPROM Memory Partitioned into Four Pages of 256 Bits ● On-Chip 512-Bit SHA-1 Engine to Compute 160- Bit Message Authentication Codes (MACs) and to Generate Secrets ● Dedicated 64-Bit Write-Only Secret with a Feature to Extend the Secret Size to 320 Bits by Setting a

1Kb Protected 1-Wire EEPROM with SHA-1 Engine

General Description The DS28E01-100 combines 1024 bits of EEPROM with challenge-and-response authentication security implemented with the ISO/IEC 10118-3 Secure Hash Algorithm (SHA-1). The 1024-bit EEPROM array is configured as four pages of 256 bits with a 64-bit scratch pad to perform write o

1K-Bit Protected 1-Wire EEPROM with SHA-1 Engine

GENERAL DESCRIPTION The DS28E01-100 combines1024 bits of EEPROM with challenge-and-response authentication security implemented with the ISO/IEC 10118-3 Secure Hash Algorithm (SHA-1). The 1024-bit EEPROM array is configured as four pages of 256 bits with a 64-bit scratchpad to perform write ope

1Kb Protected 1-Wire EEPROM with SHA-1 Engine

Features ● 1024 Bits of EEPROM Memory Partitioned into Four Pages of 256 Bits ● On-Chip 512-Bit SHA-1 Engine to Compute 160- Bit Message Authentication Codes (MACs) and to Generate Secrets ● Dedicated 64-Bit Write-Only Secret with a Feature to Extend the Secret Size to 320 Bits by Setting a

1Kb Protected 1-Wire EEPROM with SHA-1 Engine

Features ● 1024 Bits of EEPROM Memory Partitioned into Four Pages of 256 Bits ● On-Chip 512-Bit SHA-1 Engine to Compute 160- Bit Message Authentication Codes (MACs) and to Generate Secrets ● Dedicated 64-Bit Write-Only Secret with a Feature to Extend the Secret Size to 320 Bits by Setting a

1Kb Protected 1-Wire EEPROM with SHA-1 Engine

Features ● 1024 Bits of EEPROM Memory Partitioned into Four Pages of 256 Bits ● On-Chip 512-Bit SHA-1 Engine to Compute 160- Bit Message Authentication Codes (MACs) and to Generate Secrets ● Dedicated 64-Bit Write-Only Secret with a Feature to Extend the Secret Size to 320 Bits by Setting a

1Kb Protected 1-Wire EEPROM with SHA-1 Engine

Features ● 1024 Bits of EEPROM Memory Partitioned into Four Pages of 256 Bits ● On-Chip 512-Bit SHA-1 Engine to Compute 160- Bit Message Authentication Codes (MACs) and to Generate Secrets ● Dedicated 64-Bit Write-Only Secret with a Feature to Extend the Secret Size to 320 Bits by Setting a

1K-Bit Protected 1-Wire EEPROM with SHA-1 Engine

GENERAL DESCRIPTION The DS28E01-100 combines1024 bits of EEPROM with challenge-and-response authentication security implemented with the ISO/IEC 10118-3 Secure Hash Algorithm (SHA-1). The 1024-bit EEPROM array is configured as four pages of 256 bits with a 64-bit scratchpad to perform write ope

1K-Bit Protected 1-Wire EEPROM with SHA-1 Engine

GENERAL DESCRIPTION The DS28E01-100 combines1024 bits of EEPROM with challenge-and-response authentication security implemented with the ISO/IEC 10118-3 Secure Hash Algorithm (SHA-1). The 1024-bit EEPROM array is configured as four pages of 256 bits with a 64-bit scratchpad to perform write ope

1Kb Protected 1-Wire EEPROM with SHA-1 Engine

General Description The DS28E01-100 combines 1024 bits of EEPROM with challenge-and-response authentication security implemented with the ISO/IEC 10118-3 Secure Hash Algorithm (SHA-1). The 1024-bit EEPROM array is configured as four pages of 256 bits with a 64-bit scratch pad to perform write o

1K-Bit Protected 1-Wire EEPROM with SHA-1 Engine

GENERAL DESCRIPTION The DS28E01-100 combines1024 bits of EEPROM with challenge-and-response authentication security implemented with the ISO/IEC 10118-3 Secure Hash Algorithm (SHA-1). The 1024-bit EEPROM array is configured as four pages of 256 bits with a 64-bit scratchpad to perform write ope

1K-Bit Protected 1-Wire EEPROM with SHA-1 Engine

GENERAL DESCRIPTION The DS28E01-100 combines1024 bits of EEPROM with challenge-and-response authentication security implemented with the ISO/IEC 10118-3 Secure Hash Algorithm (SHA-1). The 1024-bit EEPROM array is configured as four pages of 256 bits with a 64-bit scratchpad to perform write ope

1K-Bit Protected 1-Wire EEPROM with SHA-1 Engine

GENERAL DESCRIPTION The DS28E01-100 combines1024 bits of EEPROM with challenge-and-response authentication security implemented with the ISO/IEC 10118-3 Secure Hash Algorithm (SHA-1). The 1024-bit EEPROM array is configured as four pages of 256 bits with a 64-bit scratchpad to perform write ope

1K-Bit Protected 1-Wire EEPROM with SHA-1 Engine

GENERAL DESCRIPTION The DS28E01-100 combines1024 bits of EEPROM with challenge-and-response authentication security implemented with the ISO/IEC 10118-3 Secure Hash Algorithm (SHA-1). The 1024-bit EEPROM array is configured as four pages of 256 bits with a 64-bit scratchpad to perform write ope

1Kb Protected 1-Wire EEPROM with SHA-1 Engine

General Description The DS28E01-100 combines 1024 bits of EEPROM with challenge-and-response authentication security implemented with the ISO/IEC 10118-3 Secure Hash Algorithm (SHA-1). The 1024-bit EEPROM array is configured as four pages of 256 bits with a 64-bit scratch pad to perform write o

1Kb Protected 1-Wire EEPROM with SHA-1 Engine

Features ● 1024 Bits of EEPROM Memory Partitioned into Four Pages of 256 Bits ● On-Chip 512-Bit SHA-1 Engine to Compute 160- Bit Message Authentication Codes (MACs) and to Generate Secrets ● Dedicated 64-Bit Write-Only Secret with a Feature to Extend the Secret Size to 320 Bits by Setting a

1K-Bit Protected 1-Wire EEPROM with SHA-1 Engine

GENERAL DESCRIPTION The DS28E01-100 combines1024 bits of EEPROM with challenge-and-response authentication security implemented with the ISO/IEC 10118-3 Secure Hash Algorithm (SHA-1). The 1024-bit EEPROM array is configured as four pages of 256 bits with a 64-bit scratchpad to perform write ope

1K-Bit Protected 1-Wire EEPROM with SHA-1 Engine

GENERAL DESCRIPTION The DS28E01-100 combines1024 bits of EEPROM with challenge-and-response authentication security implemented with the ISO/IEC 10118-3 Secure Hash Algorithm (SHA-1). The 1024-bit EEPROM array is configured as four pages of 256 bits with a 64-bit scratchpad to perform write ope

1Kb Protected 1-Wire EEPROM with SHA-1 Engine

Features ● 1024 Bits of EEPROM Memory Partitioned into Four Pages of 256 Bits ● On-Chip 512-Bit SHA-1 Engine to Compute 160- Bit Message Authentication Codes (MACs) and to Generate Secrets ● Dedicated 64-Bit Write-Only Secret with a Feature to Extend the Secret Size to 320 Bits by Setting a

1Kb Protected 1-Wire EEPROM with SHA-1 Engine

General Description The DS28E01-100 combines 1024 bits of EEPROM with challenge-and-response authentication security implemented with the ISO/IEC 10118-3 Secure Hash Algorithm (SHA-1). The 1024-bit EEPROM array is configured as four pages of 256 bits with a 64-bit scratch pad to perform write o

1K-Bit Protected 1-Wire EEPROM with SHA-1 Engine

GENERAL DESCRIPTION The DS28E01-100 combines1024 bits of EEPROM with challenge-and-response authentication security implemented with the ISO/IEC 10118-3 Secure Hash Algorithm (SHA-1). The 1024-bit EEPROM array is configured as four pages of 256 bits with a 64-bit scratchpad to perform write ope

1K-Bit Protected 1-Wire EEPROM with SHA-1 Engine

GENERAL DESCRIPTION The DS28E01-100 combines1024 bits of EEPROM with challenge-and-response authentication security implemented with the ISO/IEC 10118-3 Secure Hash Algorithm (SHA-1). The 1024-bit EEPROM array is configured as four pages of 256 bits with a 64-bit scratchpad to perform write ope

1Kb Protected 1-Wire EEPROM with SHA-1 Engine

Features ● 1024 Bits of EEPROM Memory Partitioned into Four Pages of 256 Bits ● On-Chip 512-Bit SHA-1 Engine to Compute 160- Bit Message Authentication Codes (MACs) and to Generate Secrets ● Dedicated 64-Bit Write-Only Secret with a Feature to Extend the Secret Size to 320 Bits by Setting a

1Kb Protected 1-Wire EEPROM with SHA-1 Engine

Features ● 1024 Bits of EEPROM Memory Partitioned into Four Pages of 256 Bits ● On-Chip 512-Bit SHA-1 Engine to Compute 160- Bit Message Authentication Codes (MACs) and to Generate Secrets ● Dedicated 64-Bit Write-Only Secret with a Feature to Extend the Secret Size to 320 Bits by Setting a

1Kb Protected 1-Wire EEPROM with SHA-1 Engine

General Description The DS28E01-100 combines 1024 bits of EEPROM with challenge-and-response authentication security implemented with the ISO/IEC 10118-3 Secure Hash Algorithm (SHA-1). The 1024-bit EEPROM array is configured as four pages of 256 bits with a 64-bit scratch pad to perform write o

1K-Bit Protected 1-Wire EEPROM with SHA-1 Engine

GENERAL DESCRIPTION The DS28E01-100 combines1024 bits of EEPROM with challenge-and-response authentication security implemented with the ISO/IEC 10118-3 Secure Hash Algorithm (SHA-1). The 1024-bit EEPROM array is configured as four pages of 256 bits with a 64-bit scratchpad to perform write ope

1K-Bit Protected 1-Wire EEPROM with SHA-1 Engine

GENERAL DESCRIPTION The DS28E01-100 combines1024 bits of EEPROM with challenge-and-response authentication security implemented with the ISO/IEC 10118-3 Secure Hash Algorithm (SHA-1). The 1024-bit EEPROM array is configured as four pages of 256 bits with a 64-bit scratchpad to perform write ope

1-Wire SHA-1 Authenticated 1Kb EEPROM with 1.8V Operation

General Description The DS28E02 combines 1024 bits of EEPROM with challenge-and-response authentication security implemented with the FIPS 180-3 Secure Hash Algorithm (SHA-1). The 1024-bit EEPROM array is configured as four pages of 256 bits with a 64-bit scratchpad to perform write operations.

1-Wire SHA-1 Authenticated 1Kb EEPROM with 1.8V Operation

General Description The DS28E02 combines 1024 bits of EEPROM with challenge-and-response authentication security implemented with the FIPS 180-3 Secure Hash Algorithm (SHA-1). The 1024-bit EEPROM array is configured as four pages of 256 bits with a 64-bit scratchpad to perform write operations.

1-Wire SHA-1 Authenticated 1Kb EEPROM with 1.8V Operation

General Description The DS28E02 combines 1024 bits of EEPROM with challenge-and-response authentication security implemented with the FIPS 180-3 Secure Hash Algorithm (SHA-1). The 1024-bit EEPROM array is configured as four pages of 256 bits with a 64-bit scratchpad to perform write operations.

1-Wire SHA-1 Authenticated 1Kb EEPROM with 1.8V Operation

General Description The DS28E02 combines 1024 bits of EEPROM with challenge-and-response authentication security implemented with the FIPS 180-3 Secure Hash Algorithm (SHA-1). The 1024-bit EEPROM array is configured as four pages of 256 bits with a 64-bit scratchpad to perform write operations.

4096-Bit Addressable 1-Wire EEPROM with PIO

GENERAL DESCRIPTION The DS28E04-100 is a 4096-bit, 1-Wire® EEPROM chip with seven address inputs. The address inputs are directly mapped into the 1-Wire 64-bit Device ID Number to easily enable the host system to identify the physical location or functional association of the DS28E04-100 in a mul

4096-Bit Addressable 1-Wire EEPROM with PIO

GENERAL DESCRIPTION The DS28E04-100 is a 4096-bit, 1-Wire® EEPROM chip with seven address inputs. The address inputs are directly mapped into the 1-Wire 64-bit Device ID Number to easily enable the host system to identify the physical location or functional association of the DS28E04-100 in a mul

4096-Bit Addressable 1-Wire EEPROM with PIO

GENERAL DESCRIPTION The DS28E04-100 is a 4096-bit, 1-Wire® EEPROM chip with seven address inputs. The address inputs are directly mapped into the 1-Wire 64-bit Device ID Number to easily enable the host system to identify the physical location or functional association of the DS28E04-100 in a mul

Single-Contact 1-Wire Interface

General Description The DS28E05 is a 112-byte user-programmable EEPROM organized as 7 pages of 16 bytes each. Memory pages can be individually set to write protected or EPROM emulation mode through protection byte settings. Each part has its own guaranteed unique 64-bit ROM identification numbe