SBR 肖特基二极管

Low Differential Pressure Gases

Description: The Magnehelic® gauge uses magnetic coupling from the movement of a silicon rubber diaphragm onto a helical pointer drive shaft. This measurement is friction free, accurate at very low differential pressures, and resistant to shock and vibration. The standard aluminum housing can be

Differential Pressure Gauge with Alarms

Description: Based on the Magnehelic® design, this gauge retains the low DP sensitivity and accuracy whilst adding two relay outputs for high and low DP alarms. The Photohelic® principle uses the standard gauge pointer to interrupt infra-red beams at the adjustable set points, which then drive th

Differential Pressure Gauge with Transmitter

Description: The standard, easy to read Magnehelic® dial gauge gives local indication of very low differential pressures in air or gas applications. Additionally, a two-wire 4-20mA transmission is provided from a built in strain gauge DP monitor, allowing remote monitoring or control. Span and ze

1-Wire Digital Potentiometer

FEATURES ● Single element 256-position linear taper potentiometer ● Supports potentiometer terminal working voltages up to 11V ● Potentiometer terminal voltage independent of supply voltage ● Potentiometer wiper position controlled and read over minimal 1-Wire bus interface ● 100 kΩ

1-Wire Digital Potentiometer

FEATURES ● Single element 256-position linear taper potentiometer ● Supports potentiometer terminal working voltages up to 11V ● Potentiometer terminal voltage independent of supply voltage ● Potentiometer wiper position controlled and read over minimal 1-Wire bus interface ● 100 kΩ

1-Wire Digital Potentiometer

FEATURES ● Single element 256-position linear taper potentiometer ● Supports potentiometer terminal working voltages up to 11V ● Potentiometer terminal voltage independent of supply voltage ● Potentiometer wiper position controlled and read over minimal 1-Wire bus interface ● 100 kΩ

1-Wire Digital Potentiometer

FEATURES ● Single element 256-position linear taper potentiometer ● Supports potentiometer terminal working voltages up to 11V ● Potentiometer terminal voltage independent of supply voltage ● Potentiometer wiper position controlled and read over minimal 1-Wire bus interface ● 100 kΩ

1-Wire Digital Potentiometer

FEATURES ● Single element 256-position linear taper potentiometer ● Supports potentiometer terminal working voltages up to 11V ● Potentiometer terminal voltage independent of supply voltage ● Potentiometer wiper position controlled and read over minimal 1-Wire bus interface ● 100 kΩ

1-Wire Digital Potentiometer

FEATURES ● Single element 256-position linear taper potentiometer ● Supports potentiometer terminal working voltages up to 11V ● Potentiometer terminal voltage independent of supply voltage ● Potentiometer wiper position controlled and read over minimal 1-Wire bus interface ● 100 kΩ

1-Wire Digital Potentiometer

FEATURES ● Single element 256-position linear taper potentiometer ● Supports potentiometer terminal working voltages up to 11V ● Potentiometer terminal voltage independent of supply voltage ● Potentiometer wiper position controlled and read over minimal 1-Wire bus interface ● 100 kΩ

1-Wire Digital Potentiometer

FEATURES ● Single element 256-position linear taper potentiometer ● Supports potentiometer terminal working voltages up to 11V ● Potentiometer terminal voltage independent of supply voltage ● Potentiometer wiper position controlled and read over minimal 1-Wire bus interface ● 100 kΩ

1-Wire Digital Potentiometer

FEATURES ● Single element 256-position linear taper potentiometer ● Supports potentiometer terminal working voltages up to 11V ● Potentiometer terminal voltage independent of supply voltage ● Potentiometer wiper position controlled and read over minimal 1-Wire bus interface ● 100 kΩ

1-Wire Digital Potentiometer

FEATURES ● Single element 256-position linear taper potentiometer ● Supports potentiometer terminal working voltages up to 11V ● Potentiometer terminal voltage independent of supply voltage ● Potentiometer wiper position controlled and read over minimal 1-Wire bus interface ● 100 kΩ

I2C Low-Voltage SHA-3 Authenticator

Benefits and Features ● Robust Countermeasures Protect Against Security Attacks • All Stored Data Cryptographically Protected from Discovery ● Efficient Secure Hash Algorithm to Authenticate Peripherals • FIPS 202-Compliant SHA-3 Algorithm for Challenge/Response Authentication • FIPS 198-

I2C Low-Voltage SHA-3 Authenticator

Benefits and Features ● Robust Countermeasures Protect Against Security Attacks • All Stored Data Cryptographically Protected from Discovery ● Efficient Secure Hash Algorithm to Authenticate Peripherals • FIPS 202-Compliant SHA-3 Algorithm for Challenge/Response Authentication • FIPS 198-

DeepCover Secure Authenticator

Benefits and Features ● ECC-256 Compute Engine • FIPS 186 ECDSA P256 Signature and Verification • ECDH Key Exchange with Authentication Prevents Man-in-the-Middle Attacks • ECDSA Authenticated R/W of Configurable Memory ● FIPS 180 SHA-256 Compute Engine • HMAC ● SHA-256 OTP (One-Time Pad)

DeepCover Secure ECDSA Bidirectional Authenticator with ChipDNA PUF Protection

Benefits and Features ● Robust Countermeasures Protect Against Security Attacks • Patented Physically Unclonable Function Secures Device Data • Actively Monitored Die Shield Detects and Reacts to Intrusion Attempts • All Stored Data Cryptographically Protected from Discovery ● ECDSA Authe

DeepCover Secure ECDSA Bidirectional Authenticator with ChipDNA PUF Protection

Benefits and Features ● Robust Countermeasures Protect Against Security Attacks • Patented Physically Unclonable Function Secures Device Data • Actively Monitored Die Shield Detects and Reacts to Intrusion Attempts • All Stored Data Cryptographically Protected from Discovery ● ECDSA Authe

1K-Bit Protected 1-Wire EEPROM with SHA-1 Engine

GENERAL DESCRIPTION The DS28E01-100 combines1024 bits of EEPROM with challenge-and-response authentication security implemented with the ISO/IEC 10118-3 Secure Hash Algorithm (SHA-1). The 1024-bit EEPROM array is configured as four pages of 256 bits with a 64-bit scratchpad to perform write ope

1Kb Protected 1-Wire EEPROM with SHA-1 Engine

General Description The DS28E01-100 combines 1024 bits of EEPROM with challenge-and-response authentication security implemented with the ISO/IEC 10118-3 Secure Hash Algorithm (SHA-1). The 1024-bit EEPROM array is configured as four pages of 256 bits with a 64-bit scratch pad to perform write o

1Kb Protected 1-Wire EEPROM with SHA-1 Engine

Features ● 1024 Bits of EEPROM Memory Partitioned into Four Pages of 256 Bits ● On-Chip 512-Bit SHA-1 Engine to Compute 160- Bit Message Authentication Codes (MACs) and to Generate Secrets ● Dedicated 64-Bit Write-Only Secret with a Feature to Extend the Secret Size to 320 Bits by Setting a

1Kb Protected 1-Wire EEPROM with SHA-1 Engine

Features ● 1024 Bits of EEPROM Memory Partitioned into Four Pages of 256 Bits ● On-Chip 512-Bit SHA-1 Engine to Compute 160- Bit Message Authentication Codes (MACs) and to Generate Secrets ● Dedicated 64-Bit Write-Only Secret with a Feature to Extend the Secret Size to 320 Bits by Setting a

1Kb Protected 1-Wire EEPROM with SHA-1 Engine

Features ● 1024 Bits of EEPROM Memory Partitioned into Four Pages of 256 Bits ● On-Chip 512-Bit SHA-1 Engine to Compute 160- Bit Message Authentication Codes (MACs) and to Generate Secrets ● Dedicated 64-Bit Write-Only Secret with a Feature to Extend the Secret Size to 320 Bits by Setting a

1Kb Protected 1-Wire EEPROM with SHA-1 Engine

Features ● 1024 Bits of EEPROM Memory Partitioned into Four Pages of 256 Bits ● On-Chip 512-Bit SHA-1 Engine to Compute 160- Bit Message Authentication Codes (MACs) and to Generate Secrets ● Dedicated 64-Bit Write-Only Secret with a Feature to Extend the Secret Size to 320 Bits by Setting a

1Kb Protected 1-Wire EEPROM with SHA-1 Engine

Features ● 1024 Bits of EEPROM Memory Partitioned into Four Pages of 256 Bits ● On-Chip 512-Bit SHA-1 Engine to Compute 160- Bit Message Authentication Codes (MACs) and to Generate Secrets ● Dedicated 64-Bit Write-Only Secret with a Feature to Extend the Secret Size to 320 Bits by Setting a

1K-Bit Protected 1-Wire EEPROM with SHA-1 Engine

GENERAL DESCRIPTION The DS28E01-100 combines1024 bits of EEPROM with challenge-and-response authentication security implemented with the ISO/IEC 10118-3 Secure Hash Algorithm (SHA-1). The 1024-bit EEPROM array is configured as four pages of 256 bits with a 64-bit scratchpad to perform write ope

1K-Bit Protected 1-Wire EEPROM with SHA-1 Engine

GENERAL DESCRIPTION The DS28E01-100 combines1024 bits of EEPROM with challenge-and-response authentication security implemented with the ISO/IEC 10118-3 Secure Hash Algorithm (SHA-1). The 1024-bit EEPROM array is configured as four pages of 256 bits with a 64-bit scratchpad to perform write ope

1Kb Protected 1-Wire EEPROM with SHA-1 Engine

General Description The DS28E01-100 combines 1024 bits of EEPROM with challenge-and-response authentication security implemented with the ISO/IEC 10118-3 Secure Hash Algorithm (SHA-1). The 1024-bit EEPROM array is configured as four pages of 256 bits with a 64-bit scratch pad to perform write o

1K-Bit Protected 1-Wire EEPROM with SHA-1 Engine

GENERAL DESCRIPTION The DS28E01-100 combines1024 bits of EEPROM with challenge-and-response authentication security implemented with the ISO/IEC 10118-3 Secure Hash Algorithm (SHA-1). The 1024-bit EEPROM array is configured as four pages of 256 bits with a 64-bit scratchpad to perform write ope

1K-Bit Protected 1-Wire EEPROM with SHA-1 Engine

GENERAL DESCRIPTION The DS28E01-100 combines1024 bits of EEPROM with challenge-and-response authentication security implemented with the ISO/IEC 10118-3 Secure Hash Algorithm (SHA-1). The 1024-bit EEPROM array is configured as four pages of 256 bits with a 64-bit scratchpad to perform write ope

1K-Bit Protected 1-Wire EEPROM with SHA-1 Engine

GENERAL DESCRIPTION The DS28E01-100 combines1024 bits of EEPROM with challenge-and-response authentication security implemented with the ISO/IEC 10118-3 Secure Hash Algorithm (SHA-1). The 1024-bit EEPROM array is configured as four pages of 256 bits with a 64-bit scratchpad to perform write ope

1K-Bit Protected 1-Wire EEPROM with SHA-1 Engine

GENERAL DESCRIPTION The DS28E01-100 combines1024 bits of EEPROM with challenge-and-response authentication security implemented with the ISO/IEC 10118-3 Secure Hash Algorithm (SHA-1). The 1024-bit EEPROM array is configured as four pages of 256 bits with a 64-bit scratchpad to perform write ope

1Kb Protected 1-Wire EEPROM with SHA-1 Engine

General Description The DS28E01-100 combines 1024 bits of EEPROM with challenge-and-response authentication security implemented with the ISO/IEC 10118-3 Secure Hash Algorithm (SHA-1). The 1024-bit EEPROM array is configured as four pages of 256 bits with a 64-bit scratch pad to perform write o

1Kb Protected 1-Wire EEPROM with SHA-1 Engine

Features ● 1024 Bits of EEPROM Memory Partitioned into Four Pages of 256 Bits ● On-Chip 512-Bit SHA-1 Engine to Compute 160- Bit Message Authentication Codes (MACs) and to Generate Secrets ● Dedicated 64-Bit Write-Only Secret with a Feature to Extend the Secret Size to 320 Bits by Setting a

1K-Bit Protected 1-Wire EEPROM with SHA-1 Engine

GENERAL DESCRIPTION The DS28E01-100 combines1024 bits of EEPROM with challenge-and-response authentication security implemented with the ISO/IEC 10118-3 Secure Hash Algorithm (SHA-1). The 1024-bit EEPROM array is configured as four pages of 256 bits with a 64-bit scratchpad to perform write ope

1K-Bit Protected 1-Wire EEPROM with SHA-1 Engine

GENERAL DESCRIPTION The DS28E01-100 combines1024 bits of EEPROM with challenge-and-response authentication security implemented with the ISO/IEC 10118-3 Secure Hash Algorithm (SHA-1). The 1024-bit EEPROM array is configured as four pages of 256 bits with a 64-bit scratchpad to perform write ope

1Kb Protected 1-Wire EEPROM with SHA-1 Engine

Features ● 1024 Bits of EEPROM Memory Partitioned into Four Pages of 256 Bits ● On-Chip 512-Bit SHA-1 Engine to Compute 160- Bit Message Authentication Codes (MACs) and to Generate Secrets ● Dedicated 64-Bit Write-Only Secret with a Feature to Extend the Secret Size to 320 Bits by Setting a

1Kb Protected 1-Wire EEPROM with SHA-1 Engine

General Description The DS28E01-100 combines 1024 bits of EEPROM with challenge-and-response authentication security implemented with the ISO/IEC 10118-3 Secure Hash Algorithm (SHA-1). The 1024-bit EEPROM array is configured as four pages of 256 bits with a 64-bit scratch pad to perform write o

1K-Bit Protected 1-Wire EEPROM with SHA-1 Engine

GENERAL DESCRIPTION The DS28E01-100 combines1024 bits of EEPROM with challenge-and-response authentication security implemented with the ISO/IEC 10118-3 Secure Hash Algorithm (SHA-1). The 1024-bit EEPROM array is configured as four pages of 256 bits with a 64-bit scratchpad to perform write ope

1K-Bit Protected 1-Wire EEPROM with SHA-1 Engine

GENERAL DESCRIPTION The DS28E01-100 combines1024 bits of EEPROM with challenge-and-response authentication security implemented with the ISO/IEC 10118-3 Secure Hash Algorithm (SHA-1). The 1024-bit EEPROM array is configured as four pages of 256 bits with a 64-bit scratchpad to perform write ope

1Kb Protected 1-Wire EEPROM with SHA-1 Engine

Features ● 1024 Bits of EEPROM Memory Partitioned into Four Pages of 256 Bits ● On-Chip 512-Bit SHA-1 Engine to Compute 160- Bit Message Authentication Codes (MACs) and to Generate Secrets ● Dedicated 64-Bit Write-Only Secret with a Feature to Extend the Secret Size to 320 Bits by Setting a

1Kb Protected 1-Wire EEPROM with SHA-1 Engine

Features ● 1024 Bits of EEPROM Memory Partitioned into Four Pages of 256 Bits ● On-Chip 512-Bit SHA-1 Engine to Compute 160- Bit Message Authentication Codes (MACs) and to Generate Secrets ● Dedicated 64-Bit Write-Only Secret with a Feature to Extend the Secret Size to 320 Bits by Setting a

1Kb Protected 1-Wire EEPROM with SHA-1 Engine

General Description The DS28E01-100 combines 1024 bits of EEPROM with challenge-and-response authentication security implemented with the ISO/IEC 10118-3 Secure Hash Algorithm (SHA-1). The 1024-bit EEPROM array is configured as four pages of 256 bits with a 64-bit scratch pad to perform write o

1K-Bit Protected 1-Wire EEPROM with SHA-1 Engine

GENERAL DESCRIPTION The DS28E01-100 combines1024 bits of EEPROM with challenge-and-response authentication security implemented with the ISO/IEC 10118-3 Secure Hash Algorithm (SHA-1). The 1024-bit EEPROM array is configured as four pages of 256 bits with a 64-bit scratchpad to perform write ope

1K-Bit Protected 1-Wire EEPROM with SHA-1 Engine

GENERAL DESCRIPTION The DS28E01-100 combines1024 bits of EEPROM with challenge-and-response authentication security implemented with the ISO/IEC 10118-3 Secure Hash Algorithm (SHA-1). The 1024-bit EEPROM array is configured as four pages of 256 bits with a 64-bit scratchpad to perform write ope

1-Wire SHA-1 Authenticated 1Kb EEPROM with 1.8V Operation

General Description The DS28E02 combines 1024 bits of EEPROM with challenge-and-response authentication security implemented with the FIPS 180-3 Secure Hash Algorithm (SHA-1). The 1024-bit EEPROM array is configured as four pages of 256 bits with a 64-bit scratchpad to perform write operations.

1-Wire SHA-1 Authenticated 1Kb EEPROM with 1.8V Operation

General Description The DS28E02 combines 1024 bits of EEPROM with challenge-and-response authentication security implemented with the FIPS 180-3 Secure Hash Algorithm (SHA-1). The 1024-bit EEPROM array is configured as four pages of 256 bits with a 64-bit scratchpad to perform write operations.

1-Wire SHA-1 Authenticated 1Kb EEPROM with 1.8V Operation

General Description The DS28E02 combines 1024 bits of EEPROM with challenge-and-response authentication security implemented with the FIPS 180-3 Secure Hash Algorithm (SHA-1). The 1024-bit EEPROM array is configured as four pages of 256 bits with a 64-bit scratchpad to perform write operations.

1-Wire SHA-1 Authenticated 1Kb EEPROM with 1.8V Operation

General Description The DS28E02 combines 1024 bits of EEPROM with challenge-and-response authentication security implemented with the FIPS 180-3 Secure Hash Algorithm (SHA-1). The 1024-bit EEPROM array is configured as four pages of 256 bits with a 64-bit scratchpad to perform write operations.

4096-Bit Addressable 1-Wire EEPROM with PIO

GENERAL DESCRIPTION The DS28E04-100 is a 4096-bit, 1-Wire® EEPROM chip with seven address inputs. The address inputs are directly mapped into the 1-Wire 64-bit Device ID Number to easily enable the host system to identify the physical location or functional association of the DS28E04-100 in a mul

4096-Bit Addressable 1-Wire EEPROM with PIO

GENERAL DESCRIPTION The DS28E04-100 is a 4096-bit, 1-Wire® EEPROM chip with seven address inputs. The address inputs are directly mapped into the 1-Wire 64-bit Device ID Number to easily enable the host system to identify the physical location or functional association of the DS28E04-100 in a mul

4096-Bit Addressable 1-Wire EEPROM with PIO

GENERAL DESCRIPTION The DS28E04-100 is a 4096-bit, 1-Wire® EEPROM chip with seven address inputs. The address inputs are directly mapped into the 1-Wire 64-bit Device ID Number to easily enable the host system to identify the physical location or functional association of the DS28E04-100 in a mul

Single-Contact 1-Wire Interface

General Description The DS28E05 is a 112-byte user-programmable EEPROM organized as 7 pages of 16 bytes each. Memory pages can be individually set to write protected or EPROM emulation mode through protection byte settings. Each part has its own guaranteed unique 64-bit ROM identification numbe

Single-Contact 1-Wire Interface

General Description The DS28E05 is a 112-byte user-programmable EEPROM organized as 7 pages of 16 bytes each. Memory pages can be individually set to write protected or EPROM emulation mode through protection byte settings. Each part has its own guaranteed unique 64-bit ROM identification numbe

Single-Contact 1-Wire Interface

General Description The DS28E05 is a 112-byte user-programmable EEPROM organized as 7 pages of 16 bytes each. Memory pages can be individually set to write protected or EPROM emulation mode through protection byte settings. Each part has its own guaranteed unique 64-bit ROM identification numbe

Single-Contact 1-Wire Interface

General Description The DS28E05 is a 112-byte user-programmable EEPROM organized as 7 pages of 16 bytes each. Memory pages can be individually set to write protected or EPROM emulation mode through protection byte settings. Each part has its own guaranteed unique 64-bit ROM identification numbe

1024-Bit, 1-Wire EEPROM

General Description The DS28E07 is a 1024-bit, 1-Wire® EEPROM chip organized as four memory pages of 256 bits each. Data is written to an 8-byte scratchpad, verified, and then copied to the EEPROM memory. As a special feature, the four user memory pages can individually be write protected or

1024-Bit, 1-Wire EEPROM

General Description The DS28E07 is a 1024-bit, 1-Wire® EEPROM chip organized as four memory pages of 256 bits each. Data is written to an 8-byte scratchpad, verified, and then copied to the EEPROM memory. As a special feature, the four user memory pages can individually be write protected or

1024-Bit, 1-Wire EEPROM

General Description The DS28E07 is a 1024-bit, 1-Wire® EEPROM chip organized as four memory pages of 256 bits each. Data is written to an 8-byte scratchpad, verified, and then copied to the EEPROM memory. As a special feature, the four user memory pages can individually be write protected or