DS26C32AMQML Quad Differential Line Receiver

FEATURES • CMOS Design for Low Power • ±0.2V Sensitivity Over Input Common Mode Voltage Range • Input Fail-Safe Circuitry • Inputs Won't Load Line When VCC = 0V • Meets the Requirements of EIA Standard RS- 422 pull• TRI-STATE Outputs for Connection to System Buses DESCRIPTION The DS26

CMOS 四路差动线路接收器

The DS26C32A is a quad differential line receiver designed to meet the RS-422, RS-423, and Federal Standards 1020 and 1030 for balanced and unbalanced digital data transmission, while retaining the low power characteristics of CMOS. The DS26C32A has an input sensitivity of 200 mV over the common mod • CMOS Design for Low Power\n• ±0.2V Sensitivity Over Input Common Mode Voltage Range\n• Input Fail-Safe Circuitry\n• Inputs Won't Load Line When VCC = 0V\n• Meets the Requirements of EIA Standard RS-422 \n• TRI-STATE Outputs for Connection to System Buses;

DS26C32AMQML Quad Differential Line Receiver

文件：410.25 Kbytes Page：16 Pages

DS26C32AMQML Quad Differential Line Receiver

文件：618.09 Kbytes Page：16 Pages

DS26C32AMQML Quad Differential Line Receiver

文件：618.09 Kbytes Page：16 Pages

Quad Differential Line Receiver

文件：311.3 Kbytes Page：11 Pages

Quad Differential Line Receiver

文件：311.3 Kbytes Page：11 Pages

Quad Differential Line Receiver

文件：311.3 Kbytes Page：11 Pages

QUADRUPLE DIFFERENTIAL LINE RECEIVERS

文件：106.09 Kbytes Page：17 Pages

QUADRUPLE DIFFERENTIAL LINE RECEIVERS

文件：106.09 Kbytes Page：17 Pages