DS25BR110 3.125 Gbps LVDS Buffer with Receive Equalization

1FEATURES 2• DC - 3.125 Gbps Low Jitter, High Noise Immunity, Low Power Operation • Four Levels of Receive Equalization Reduce ISI Jitter • On-Chip 100Ω Input and Output Termination Minimizes Insertion and Return Losses, Reduces Component Count, and Minimizes Board Space • 7 kV ESD on LVD

DS25BR100 / DS25BR101 3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis and Receive Equalization

1FEATURES 2• DC - 3.125 Gbps Low Jitter, High Noise Immunity, Low Power Operation • Receive Equalization Reduces ISI Jitter Due to Media Loss • Transmit Pre-Emphasis Drives Lossy Backplanes and Cables • On-Chip 100Ω Input and Output Termination: – Minimizes Insertion and Return Losses – R

3.125 Gbps LVDS Buffer with Receive Equalization

文件：434.57 Kbytes Page：16 Pages

3.125 Gbps LVDS Buffer with Receive Equalization

文件：884.02 Kbytes Page：18 Pages

DS25BR110 3.125 Gbps LVDS Buffer with Receive Equalization

1FEATURES 2• DC - 3.125 Gbps Low Jitter, High Noise Immunity, Low Power Operation • Four Levels of Receive Equalization Reduce ISI Jitter • On-Chip 100Ω Input and Output Termination Minimizes Insertion and Return Losses, Reduces Component Count, and Minimizes Board Space • 7 kV ESD on LVD

DS25BR110 3.125 Gbps LVDS Buffer with Receive Equalization

1FEATURES 2• DC - 3.125 Gbps Low Jitter, High Noise Immunity, Low Power Operation • Four Levels of Receive Equalization Reduce ISI Jitter • On-Chip 100Ω Input and Output Termination Minimizes Insertion and Return Losses, Reduces Component Count, and Minimizes Board Space • 7 kV ESD on LVD

DS25BR110 3.125 Gbps LVDS Buffer with Receive Equalization

1FEATURES 2• DC - 3.125 Gbps Low Jitter, High Noise Immunity, Low Power Operation • Four Levels of Receive Equalization Reduce ISI Jitter • On-Chip 100Ω Input and Output Termination Minimizes Insertion and Return Losses, Reduces Component Count, and Minimizes Board Space • 7 kV ESD on LVD

DS25BR110 3.125 Gbps LVDS Buffer with Receive Equalization

1FEATURES 2• DC - 3.125 Gbps Low Jitter, High Noise Immunity, Low Power Operation • Four Levels of Receive Equalization Reduce ISI Jitter • On-Chip 100Ω Input and Output Termination Minimizes Insertion and Return Losses, Reduces Component Count, and Minimizes Board Space • 7 kV ESD on LVD

封装/外壳：8-WFDFN 裸露焊盘 包装：卷带（TR） 描述：IC REDRIVER LVDS 1CH 8WSON 集成电路（IC） 信号缓冲器、中继器、分离器

3.125 Gbps LVDS Buffer with Receive Equalization

文件：884.02 Kbytes Page：18 Pages

3.125 Gbps LVDS Buffer with Receive Equalization

文件：884.02 Kbytes Page：18 Pages

3.125 Gbps LVDS Buffer with Receive Equalization

文件：434.57 Kbytes Page：16 Pages