3.3V Bit Error Rate Tester BERT

DESCRIPTION The DS21372 Bit Error Rate Tester (BERT) is a software programmable test pattern generator, receiver, and analyzer capable of meeting the most stringent error performance requirements of digital transmission facilities. Two categories of test pattern generation (Pseudo-random and Repe

3.3V、位误码率测试器(BERT)

The DS21372 Bit Error Rate Tester (BERT) is a software-programmable test pattern generator, receiver, and analyzer capable of meeting the most stringent error performance requirements of digital transmission facilities. Two categories of test pattern generation (pseudorandom and repetitive) conform \n• Generates/detects digital bit patterns for analyzing, evaluating, and troubleshooting digital communications systems \n• Operates at speeds from DC to 20MHz \n• Programmable polynomial length and feedback taps for generation of any other pseudorandom pattern up to 32 bits in length including: 26;

3.3V Bit Error Rate Tester (BERT)

文件：180.64 Kbytes Page：22 Pages

3.3V Bit Error Rate Tester BERT

DESCRIPTION The DS21372 Bit Error Rate Tester (BERT) is a software programmable test pattern generator, receiver, and analyzer capable of meeting the most stringent error performance requirements of digital transmission facilities. Two categories of test pattern generation (Pseudo-random and Repe

3.3V Bit Error Rate Tester BERT

DESCRIPTION The DS21372 Bit Error Rate Tester (BERT) is a software programmable test pattern generator, receiver, and analyzer capable of meeting the most stringent error performance requirements of digital transmission facilities. Two categories of test pattern generation (Pseudo-random and Repe

3.3V Bit Error Rate Tester (BERT)

文件：180.64 Kbytes Page：22 Pages

封装/外壳：32-TQFP 功能：位误码率测试器（BERT） 包装：卷带（TR） 描述：IC TELECOM INTERFACE 32TQFP 集成电路（IC） 电信

封装/外壳：32-TQFP 功能：位误码率测试器（BERT） 包装：托盘 描述：IC TELECOM INTERFACE 32TQFP 集成电路（IC） 电信