Timer Clock Peripheral (TCP)

文件：381.74 Kbytes Page：26 Pages

Timer Clock Peripheral (TCP)

计时器控制外设 (TCP)

The DP8570A is intended for use in microprocessor based systems where information is required for multi-tasking, data logging or general time of day/date information. This device is implemented in low voltage silicon gate microCMOS technology to provide low standby power in battery back-up environme • Full function real time clock/calendar \n• Day of week and day of years counters\n• Parallel Resonant Oscillator\n• Two 16-bit timers \n• Programmable multi-function output\n• Power fail features \n• Power Supply Bus glitch protection\n• On-chip interrupt structure \n• Up to 44 bytes of CMOS RAM\n;

DP8570A Timer Clock Peripheral (TCP)

General Description The DP8570A is intended for use in microprocessor based systems where information is required for multi-tasking, data logging or general time of day/date information. This device is implemented in low voltage silicon gate microCMOS technology to provide low standby power i

DP8570A Timer Clock Peripheral (TCP)

General Description The DP8570A is intended for use in microprocessor based systems where information is required for multi-tasking, data logging or general time of day/date information. This device is implemented in low voltage silicon gate microCMOS technology to provide low standby power i

DP8570A Timer Clock Peripheral (TCP)

General Description The DP8570A is intended for use in microprocessor based systems where information is required for multi-tasking, data logging or general time of day/date information. This device is implemented in low voltage silicon gate microCMOS technology to provide low standby power i

DP8570A Timer Clock Peripheral (TCP)

General Description The DP8570A is intended for use in microprocessor based systems where information is required for multi-tasking, data logging or general time of day/date information. This device is implemented in low voltage silicon gate microCMOS technology to provide low standby power i

DP8570A Timer Clock Peripheral (TCP)

General Description The DP8570A is intended for use in microprocessor based systems where information is required for multi-tasking, data logging or general time of day/date information. This device is implemented in low voltage silicon gate microCMOS technology to provide low standby power i

DP8570A Timer Clock Peripheral (TCP)

General Description The DP8570A is intended for use in microprocessor based systems where information is required for multi-tasking, data logging or general time of day/date information. This device is implemented in low voltage silicon gate microCMOS technology to provide low standby power i

DP8570A Timer Clock Peripheral (TCP)

General Description The DP8570A is intended for use in microprocessor based systems where information is required for multi-tasking, data logging or general time of day/date information. This device is implemented in low voltage silicon gate microCMOS technology to provide low standby power i

DP8570A Timer Clock Peripheral

文件：423.79 Kbytes Page：28 Pages

Timer Clock Peripheral (TCP)

文件：381.74 Kbytes Page：26 Pages

DP8570A Timer Clock Peripheral

文件：423.79 Kbytes Page：28 Pages

Timer Clock Peripheral (TCP)

文件：381.74 Kbytes Page：26 Pages

DP8570A Timer Clock Peripheral

文件：423.79 Kbytes Page：28 Pages

Timer Clock Peripheral (TCP)

文件：381.74 Kbytes Page：26 Pages

DP8570A Timer Clock Peripheral

文件：423.79 Kbytes Page：28 Pages

DP8570A Timer Clock Peripheral

文件：423.79 Kbytes Page：28 Pages

封装/外壳：28-LCC（J 形引线） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC RTC CLK/CALENDAR PAR 28-PLCC 集成电路（IC） 实时时钟

DP8570A Timer Clock Peripheral

文件：423.79 Kbytes Page：28 Pages

DP8570A Timer Clock Peripheral

文件：423.79 Kbytes Page：28 Pages

封装/外壳：28-LCC（J 形引线） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC RTC TCP PAR 28-PLCC 集成电路（IC） 实时时钟

DP8570A Timer Clock Peripheral

文件：423.79 Kbytes Page：28 Pages

DP8570A Timer Clock Peripheral

文件：423.79 Kbytes Page：28 Pages

256 x 8-bit static low-voltage RAM with I2C-bus interface

GENERAL DESCRIPTION The PCF8570 is a low power static CMOS RAM, organized as 256 words by 8-bits. Addresses and data are transferred serially via a two-line bidirectional bus (I2C-bus). The built-in word address register is incremented automatically after each written or read data byte. Three ad