8G bits DDR4 SDRAM

• Features • Double-data-rate architecture: two data transfers per clock cycle. • The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture. • Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver

8G bits DDR4 SDRAM

• Features • Double-data-rate architecture: two data transfers per clock cycle. • The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture. • Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver

Kingston DDR4 DRAM for embedded applications

Kingston on-board DDR4 DRAM is designed to meet the needs of embedded applications and offers a high speed option with lower power consumption. KEY FEATURES • Double-data-rate architecture: two data transfers per clock cycle • The high-speed data transfer is realized by the 8 bits prefetch p

8G bits DDR4 SDRAM

• Features • Double-data-rate architecture: two data transfers per clock cycle. • The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture. • Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver

8G bits DDR4 SDRAM

• Features • Double-data-rate architecture: two data transfers per clock cycle. • The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture. • Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver

Kingston DDR4 DRAM for embedded applications

Kingston on-board DDR4 DRAM is designed to meet the needs of embedded applications and offers a high speed option with lower power consumption. KEY FEATURES • Double-data-rate architecture: two data transfers per clock cycle • The high-speed data transfer is realized by the 8 bits prefetch p

8G bits DDR4 SDRAM

• Features • Double-data-rate architecture: two data transfers per clock cycle. • The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture. • Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver

8G bits DDR4 SDRAM

• Features • Double-data-rate architecture: two data transfers per clock cycle. • The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture. • Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver

Modbus RTU or DGH ASCII communications protocol

文件：52.59 Kbytes Page：4 Pages

Modbus RTU or DGH ASCII communications protocol

文件：52.59 Kbytes Page：4 Pages

包装：盒 描述：PLIERS STANDARD FLAT NOSE 6.56\ 工具 钳子

DRAM 组件

DRAM 组件

DRAM 组件

包装：盒 描述：PLIERS STANDARD FLAT NOSE 8.06\ 工具 钳子

1500 MHz Low Power UltraCMOS??Divide-by-2 Prescaler

Product Description The PE3511 is a high-performance static UltraCMOS™ prescaler with a fixed divide ratio of 2. Its operating frequency range is DC to 1500 MHz. The PE3511 operates on a nominal 3 V supply and draws only 8 mA. The input and output interfaces support both AC-coupled, low-Z RF as w

COAXIAL RESONATOR OSCILLATOR

文件：57.26 Kbytes Page：1 Pages

COAXIAL RESONATOR OSCILLATOR

文件：57.26 Kbytes Page：1 Pages

Bifurcated Contacts with Solder Tail or Wire Wrap Pins

文件：526.25 Kbytes Page：1 Pages

횠12.7mm mounting Robust bright nickel plated brass housing

文件：432.85 Kbytes Page：5 Pages