288M-BIT Low Latency DRAM Common I/O

Features • SRAM-type interface • Double-data-rate architecture • PLL circuitry • Cycle time: 2.5 ns @ tRC = 20 ns 3.3 ns @ tRC = 20 ns • Non-multiplexed addresses • Multiplexing option is available. • Data mask for WRITE commands • Differential input clocks (CK and CK#) • Differential in