128M-bit Synchronous DRAM 4-bank, LVTTL

Description The µPD45128441, 45128841, 45128163 are high-speed 134,217,728-bit synchronous dynamic random-access memories, organized as 8,388,608 × 4 × 4, 4,194,304 × 8 × 4, 2,097,152 × 16 × 4 (word × bit × bank), respectively. The synchronous DRAMs achieved high-speed data transfer using the pi

128M-bit Synchronous DRAM 4-bank, LVTTL

Description The µPD45128441, 45128841, 45128163 are high-speed 134,217,728-bit synchronous dynamic random-access memories, organized as 8,388,608 × 4 × 4, 4,194,304 × 8 × 4, 2,097,152 × 16 × 4 (word × bit × bank), respectively. The synchronous DRAMs achieved high-speed data transfer using the pi

D45-R80F BL IP54 1000 HF940 60°

文件：146.91 Kbytes Page：2 Pages

D45-R93A WH IP20 1000HF 940 60°

文件：146.34 Kbytes Page：2 Pages

D45-R80F WH IP54 1000 HF930 60°

文件：173.22 Kbytes Page：2 Pages

D45-R80F WH IP54 1000DALI 930 60°

文件：173.24 Kbytes Page：2 Pages

D45-R80F WH IP54 1000 HF940 60°

文件：171.74 Kbytes Page：2 Pages

D45-R80F WH IP54 1000DALI 940 60°

文件：173.26 Kbytes Page：2 Pages

D45-R80F BL IP54 1000 HF930 60°

文件：147 Kbytes Page：2 Pages

D45-R80F BL IP54 1000DALI 930 60°

文件：146.91 Kbytes Page：2 Pages

D45-R80F BL IP54 1000DALI 940 60°

文件：146.9 Kbytes Page：2 Pages

D45-R93A WH IP20 1000HF 930 60°

文件：146.34 Kbytes Page：2 Pages

D45-R93A BL IP20 1000 HF930 60°

文件：141.74 Kbytes Page：2 Pages

D45-R93A BL IP20 1000 HF940 60°

文件：141.7 Kbytes Page：2 Pages

8-CHANNEL DATA SELECTOR

DESCRIPTION The HCC4512B (extended temperature range) and HCF4512B (intermediate temperature range) are monolithic integrated circuit, available in 16-lead dual in-line plastic or ceramic package and plastic micro package. The HCC/HCF4512B is an 8-channel data selector featuring a three-state ou

8-input multiplexer with 3-state output

DESCRIPTION The HEF4512B is an 8-input multiplexer with 8 binary inputs (I0 to I7), an enable input (E) and an output enable input (EO). One of eight binary inputs is selected by select inputs S0, S1 and S2, and is routed to the output O. A HIGH on EO causes O to assume a high impedance OFF-state

8-input multiplexer with 3-state output

DESCRIPTION The HEF4512B is an 8-input multiplexer with 8 binary inputs (I0 to I7), an enable input (E) and an output enable input (EO). One of eight binary inputs is selected by select inputs S0, S1 and S2, and is routed to the output O. A HIGH on EO causes O to assume a high impedance OFF-state

8-input multiplexer with 3-state output

DESCRIPTION The HEF4512B is an 8-input multiplexer with 8 binary inputs (I0 to I7), an enable input (E) and an output enable input (EO). One of eight binary inputs is selected by select inputs S0, S1 and S2, and is routed to the output O. A HIGH on EO causes O to assume a high impedance OFF-state

8-input multiplexer with 3-state output

DESCRIPTION The HEF4512B is an 8-input multiplexer with 8 binary inputs (I0 to I7), an enable input (E) and an output enable input (EO). One of eight binary inputs is selected by select inputs S0, S1 and S2, and is routed to the output O. A HIGH on EO causes O to assume a high impedance OFF-state