8G bits DDR4 SDRAM

• Features • Double-data-rate architecture: two data transfers per clock cycle. • The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture. • Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver

8G bits DDR4 SDRAM

• Features • Double-data-rate architecture: two data transfers per clock cycle. • The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture. • Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver

8G bits DDR4 SDRAM

• Features • Double-data-rate architecture: two data transfers per clock cycle. • The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture. • Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver

8G bits DDR4 SDRAM

• Features • Double-data-rate architecture: two data transfers per clock cycle. • The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture. • Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver

8G bits DDR4 SDRAM

• Features • Double-data-rate architecture: two data transfers per clock cycle. • The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture. • Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver