PSoC® Functional Overview

The PSoC family consists of many Programmable System-on-Chip with on-chip controller devices. These devices are designed to replace multiple traditional microcontroller unit (MCU)-based system components with one low cost single chip programmable component. A PSoC device includes configurable analog and digital blocks and programmable interconnect. This architecture enables the user to create customized peripheral configurations to match the requirements of each individual application. Additionally, a fast CPU, flash program memory, SRAM data memory, and configurable I/O are included in a range of convenient pinouts.

Features

■ Automotive Electronics Council (AEC) Q100 qualified

■ Low power CapSense® block

❐ Configurable capacitive sensing elements

❐ Supports combination of CapSense buttons, sliders, touchpads, and proximity sensors

■ Powerful Harvard-architecture processor

❐ M8C processor speeds up to 12 MHz

❐ Low power at high speed

❐ Operating voltage: 3.0 V to 5.25 V

❐ Automotive temperature range: –40 °C to +85 °C

■ Flexible on-chip memory

❐ 8 KB of flash program storage, 1000 erase/write cycles

❐ 512 bytes of SRAM data storage

❐ Partial flash updates

❐ Flexible protection modes

❐ In-system serial programming (ISSP)

■ Complete development tools

❐ Free development tool (PSoC Designer™)

❐ Full featured, in-circuit emulator (ICE) and programmer

❐ Full-speed emulation

❐ Complex breakpoint structure

❐ 128 KB trace memory

■ Precision, programmable clocking

❐ Internal ±5 6-/12-MHz oscillator

❐ Internal low-speed, low-power oscillator for watchdog and sleep functionality

■ Programmable pin configurations

❐ 20 mA sink on all general purpose I/Os (GPIOs)

❐ Pull-up, high Z, open drain, or strong drive modes on all GPIOs

❐ Up to 13 analog inputs on GPIOs

❐ Configurable interrupt on all GPIOs

❐ Selectable, regulated digital I/O on Port 1

• 3.0 V, 2.4 V, and 1.8 V regulation available

• Up to 5 mA source on Port 1 GPIOs

■ Versatile analog mux

❐ Common internal analog bus

❐ Simultaneous connection of I/O combinations

❐ Comparator noise immunity

■ Additional system resources

❐ Configurable communication speeds

• I2C™ slave operation up to 400 kHz

• SPI master or slave operation between 46.9 kHz and 12 MHz

❐ Watchdog and sleep timers

❐ Internal voltage reference

❐ Integrated supervisory circuit