Functional Description[1]

The CY7C1346H SRAM integrates 64K x 36 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK).

Features

• Registered inputs and outputs for pipelined operation

• 64K × 36 common I/O architecture

• 3.3V core power supply

• 3.3V/2.5V I/O operation

• Fast clock-to-output times

— 3.5 ns (166-MHz device)

• Provide high-performance 3-1-1-1 access rate

• User-selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed writes

• Asynchronous output enable

• Offered in JEDEC-standard lead-free 100-pin TQFP package

• “ZZ” Sleep Mode Option