Functional Description

The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced double-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high valued resistors.

Features

• Fast access times: 5, 6, 7, and 8 ns

• Fast clock speed: 100, 83, 66, and 50 MHz

• Provide high-performance 3-1-1-1 access rate

• Fast OE access times: 5 and 6 ns

• Optimal for performance (two cycle chip deselect, depth expansion without wait state)

• Single +3.3V –5 to +10 power supply

• 5V tolerant inputs except I/Os

• Clamp diodes to VSSQ at all inputs and outputs

• Common data inputs and data outputs

• Byte Write Enable and Global Write control

• Three chip enables for depth expansion and address pipeline

• Address, control, input, and output pipeline registers

• Internally self-timed Write Cycle

• Write pass-through capability

• Burst control pins (interleaved or linear burst sequence)

• Automatic power-down for portable applications

• High-density, high-speed packages

• Low capacitive bus loading

• High 30-pF output drive capability at rated access time