FEATURES GENERAL DESCRIPTION

 Compliant with DisplayPort specification version 1.2

and Embedded DisplayPort (eDP) specification version

1.3.

 Support 2 Main Link Lanes at either 1.62Gb/s or

2.7Gb/s link rate

 Support analog RGB output for VGA with Triple 9-bit

DAC up to 200MHz pixel rate. Sync signals can be

provided in separated or composite manner. Support

VESA and CEA timing standards u up to 1920x1200@

60Hz or 2048x1152@60Hz with reduced blanking

 VGA output is compliant with VESA VSIS v1r2

specification

 Embedded MCU to handle the control logic

 Support device boot up by automatically loading

firmware from on-chip flash Boot ROM

 Integrated EDID Buffer, and MCCS bypass supported

 Supports Enhanced Framing Mode

 Fast and full Link Training for embedded DisplayPort

system

 Support eDP Authentication: Alternative Scramble Seed

Reset and Alternative Framing

 2 work modes: connect 27MHz crystal, inject 27MHz

clock

 DAC connection detection supported

 DP input detection supported

 Support Auto Power Saving mode and low stand-by

current

 Support Spread Spectrum Clocking (de-spreading) for

EMI reduction

 DP AUX channel and IIC slave interface are available

for firmware update and debug

 Low power architecture

 3.3V/1.05V power supply supported for motherboard

solution design

 RoHS compliant and Halogen free package

 Offered in 40-Pin QFN package (5 x 5 mm)

APPLICATION

 Notebook/Ultrabook

 Tablet Device

 Handheld/Portable Device

 PC

Chrontel’s CH7517 is a low-cost, low-power

semiconductor device that translates the DisplayPort

signal to the VGA. This innovative DisplayPort receiver

with an integrated VGA encoder is specially designed to

target the notebook/ultrabook, tablet device and PC

market segments. Through the CH7517’s advanced

decoding / encoding algorithm, the input DisplayPort

high-speed serialized multimedia data can be seamlessly

converted to analog RGB video output.

The CH7517 is compliant with the DisplayPort

specification version 1.2 and the Embedded DisplayPort

Specification version 1.3. In the device’s receiver block,

which supports two DisplayPort Main Link Lanes input

with data rate running at either 1.62Gb/s or 2.7Gb/s, can

accept RGB digital formats in either 18-bit 6:6:6 or 24-bit

8:8:8, and converted the input signal to VGA output up to

1920x1200@ 60Hz or 2048x1152@60Hz with reduced

blanking. Leveraging the DisplayPort’s unique

source/sink “Link Training” routine, the CH7517 is

capable of instantly bring up the video display to the

VGA monitor when the initialization process is

completed between CH7517 and the graphic chip.

The DACs are based on current source architecture. And

the VGA output meet VESA VSIS v1r2 clock jitter target.

With sophisticated MCU and the on-chip Flash, CH7517

support auto-boot and EDID buffer. After the

configuration by firmware, which is auto loaded from the

Flash embedded, CH7517 supports DisplayPort input

detection, DAC connection detection and determine to

enter into power saving mode automatically.