GENERAL DESCRIPTION

50S116T is a high-speed synchronous dynamic random access memory (SDRAM), organized as 512K words ´ 2 banks ´ 16 bits. Using pipelined architecture 50S116T delivers a data bandwidth of up to 400M bytes per second (-5). For different applications the 50S116T is sorted into the following speed grades: -5, -6, -7. The -5 parts can run up to 200MHz/CL3. The -6 parts can run up to 166 MHz/CL3. The -7 parts can run up to 143 MHz/CL3. For handheld device application.

FEATURES

• 3.3V ±0.3V power supply

• Up to 200 MHz clock frequency

• 524,288 words x 2 banks x 16 bits organization

• CAS latency: 2 and 3

• Burst Length: 1, 2, 4, 8, and full page

• Burst read, Single Write Mode

• Byte data controlled by UDQM and LDQM

• Auto precharge and controlled precharge

• 4K refresh cycles/64 mS

• Interface: LVTTL

• Packaged in 50-pin, 400 mil TSOP II