144-Mbit DDR II SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency)

Functional Description The CY7C1648KV18, and CY7C1650KV18 are 1.8-V synchronous pipelined SRAMs equipped with DDR II+ architecture. The DDR II+ consists of an SRAM core with advanced synchronous peripheral circuitry. Features ■ 144-Mbit density (8 M × 18, 4 M × 36) ■ 450-MHz clock for high ban

144-Mbit DDR II SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency)

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封装/外壳：165-LBGA 包装：托盘 描述：IC SRAM 144MBIT PARALLEL 165FBGA 集成电路（IC） 存储器

双倍数据速率 (DDR) 同步 SRAM