2M x 36/4M x 18 Pipelined DCD SRAM

Functional Description[1] The CY7C1484V33/CY7C1485V33 SRAM integrates 2M x 36/4M x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. Features • Supports bus operation up to 250 MHz • Available speed grades are 250, 200, and 16

72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM

文件：1.15468 Mbytes Page：26 Pages

72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM

文件：1.15468 Mbytes Page：26 Pages

72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM

文件：1.15468 Mbytes Page：26 Pages

72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM

文件：1.15468 Mbytes Page：26 Pages

2M x 36/4M x 18 Pipelined DCD SRAM

Functional Description[1] The CY7C1484V33/CY7C1485V33 SRAM integrates 2M x 36/4M x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. Features • Supports bus operation up to 250 MHz • Available speed grades are 250, 200, and 16

2M x 36/4M x 18 Pipelined DCD SRAM

Functional Description[1] The CY7C1484V33/CY7C1485V33 SRAM integrates 2M x 36/4M x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. Features • Supports bus operation up to 250 MHz • Available speed grades are 250, 200, and 16

72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM

文件：1.15468 Mbytes Page：26 Pages

72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM

文件：1.15468 Mbytes Page：26 Pages