72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM

Functional Description The CY7C1480BV25/CY7C1482BV25/CY7C1486BV25[1] SRAM integrates 2M x 36/4M x 18/1M × 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-tr

72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM

Functional Description The CY7C1480BV25/CY7C1482BV25/CY7C1486BV25[1] SRAM integrates 2M x 36/4M x 18/1M × 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-tr

封装/外壳：100-LQFP 包装：托盘 描述：IC SRAM 72MBIT PARALLEL 100TQFP 集成电路（IC） 存储器

同步 SRAM

72-Mbit (2 M x 36/4 M x 18/1 M x 72) Pipelined Sync SRAM

文件：1.12689 Mbytes Page：34 Pages

72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM

Functional Description The CY7C1480BV25/CY7C1482BV25/CY7C1486BV25[1] SRAM integrates 2M x 36/4M x 18/1M × 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-tr

72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM

Functional Description The CY7C1480BV25/CY7C1482BV25/CY7C1486BV25[1] SRAM integrates 2M x 36/4M x 18/1M × 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-tr