9-Mbit (256K x 36/512K x 18) Pipelined SRAM

Functional Description The CY7C1360C/CY7C1362C SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock

256K x 36/512K x 18 Synchronous Pipelined Burst SRAM

Functional Description The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors. The CY7C1360A and CY7C1362A SRAMs inte

9-Mbit (256K x 36/512K x 18) Pipelined SRAM

Functional Description The CY7C1360C/CY7C1362C SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock

9-Mbit (256K x 36/512K x 18) Pipelined SRAM

Functional Description The CY7C1360C/CY7C1362C SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock

9-Mbit (256K x 36/512K x 18) Pipelined SRAM

文件：521.48 Kbytes Page：31 Pages