4 - MBIT ( 128K X 32 ) PIPELINED SYNC SRAM

Functional Description[1] The CY7C1339G SRAM integrates 128K x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous

4 - MBIT ( 128K X 32 ) PIPELINED SYNC SRAM

Functional Description[1] The CY7C1339G SRAM integrates 128K x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous

4-Mbit (128K x 32) Pipelined Sync SRAM

文件：415.08 Kbytes Page：18 Pages

4-Mbit (128 K 횞 32) Pipelined Sync SRAM

文件：629.08 Kbytes Page：21 Pages

4-Mbit (128 K x 32) Pipelined Sync SRAM

文件：645.84 Kbytes Page：22 Pages

Memories for Embedded Systems - Synchronous SRAMs - Standard Sync -

封装/外壳：100-LQFP 包装：卷带（TR） 描述：IC SRAM 4MBIT PARALLEL 100TQFP 集成电路（IC） 存储器

封装/外壳：100-LQFP 包装：卷带（TR） 描述：IC SRAM 4MBIT PARALLEL 100TQFP 集成电路（IC） 存储器

4-Mbit (128K x 32) Pipelined Sync SRAM

文件：415.08 Kbytes Page：18 Pages

4-Mbit (128K x 32) Pipelined Sync SRAM

文件：415.08 Kbytes Page：18 Pages

IC SRAM 4M PARALLEL 100TQFP

IC SRAM 4M PARALLEL 100TQFP