18-Mbit DDR-II SRAM 2-Word Burst Architecture

Features • 18-Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36) • 300-MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency • Double Data Rate (DDR) interfaces (data transferred at 600 MHz) @ 300 MHz • Two input clocks (K and K) for precise DDR timing — SRAM u

18-Mbit DDR-II SRAM 2-Word Burst Architecture

文件：515.89 Kbytes Page：28 Pages

封装/外壳：165-LBGA 包装：卷带（TR） 描述：IC SRAM 18MBIT PARALLEL 165FBGA 集成电路（IC） 存储器

18-Mbit DDR-II SRAM 2-Word Burst Architecture

文件：1.71052 Mbytes Page：31 Pages

18-Mbit DDR-II SRAM 2-Word Burst Architecture

文件：515.89 Kbytes Page：28 Pages

18-Mbit DDR-II SRAM 2-Word Burst Architecture

文件：515.89 Kbytes Page：28 Pages