256K x 18 Synchronous-Pipelined Cache RAM

Functional Description The CY7C1327B is a 3.3V, 256K by 18 synchronous-pipelined cache SRAM designed to support zero wait state secondary cache with minimal glue logic. Features • Supports 100-MHz bus for Pentium® and PowerPC™ operations with zero wait states • Fully registered inputs and outp

4-Mbit (256K x 18) Pipelined Sync SRAM

Features • Registered inputs and outputs for pipelined operation • 256K ×18 common I/O architecture • 3.3V core power supply • 3.3V / 2.5V I/O operation • Fast clock-to-output times — 2.6 ns (for 250-MHz device) — 2.6 ns (for 225-MHz device) — 2.8 ns (for 200-MHz device) — 3.5

4-Mb (256K x 18) Pipelined Sync SRAM

文件：572.91 Kbytes Page：17 Pages

4-Mbit (256K x 18) Pipelined Sync SRAM

文件：373.23 Kbytes Page：18 Pages