mini二氧化碳检测仪CM01

丝印代码：CM0102B；CMOS 8-Stage Presettable Synchronous Down Counters

Features: . Synchronous or asynchronous preset . Medium-speed operation: fc = 3.6 MHz {typ.) @ Vpp = 10 V Cascadable 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18-V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (full pac

丝印代码：CM0102B；CMOS 8-Stage Presettable Synchronous Down Counters

Features: . Synchronous or asynchronous preset . Medium-speed operation: fc = 3.6 MHz {typ.) @ Vpp = 10 V Cascadable 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18-V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (full pac

丝印代码：CM0102B；CMOS 8-Stage Presettable Synchronous Down Counters

Features: . Synchronous or asynchronous preset . Medium-speed operation: fc = 3.6 MHz {typ.) @ Vpp = 10 V Cascadable 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18-V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (full pac

丝印代码：CM0103B；CMOS 8-Stage Presettable Synchronous Down Counters

Features: . Synchronous or asynchronous preset . Medium-speed operation: fc = 3.6 MHz {typ.) @ Vpp = 10 V Cascadable 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18-V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (full pac

丝印代码：CM0103B；CMOS 8-Stage Presettable Synchronous Down Counters

Features: . Synchronous or asynchronous preset . Medium-speed operation: fc = 3.6 MHz {typ.) @ Vpp = 10 V Cascadable 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18-V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (full pac

丝印代码：CM0106B；CD40106B CMOS Hex Schmitt-Trigger Inverters

1 Features 1• Schmitt-Trigger Inputs • Hysteresis Voltage (Typical): – 0.9 V at VDD = 5 V – 2.3 V at VDD = 10 V – 3.5 V at VDD = 15 V • Noise Immunity Greater Than 50% • No Limit On Input Rise and Fall Times • Standardized, Symmetrical Output Characteristics • For Quiescent Current at

丝印代码：CM0106B；CD40106B CMOS Hex Schmitt-Trigger Inverters

1 Features 1• Schmitt-Trigger Inputs • Hysteresis Voltage (Typical): – 0.9 V at VDD = 5 V – 2.3 V at VDD = 10 V – 3.5 V at VDD = 15 V • Noise Immunity Greater Than 50% • No Limit On Input Rise and Fall Times • Standardized, Symmetrical Output Characteristics • For Quiescent Current at

丝印代码：CM0106B；CD40106B CMOS Hex Schmitt-Trigger Inverters

1 Features 1• Schmitt-Trigger Inputs • Hysteresis Voltage (Typical): – 0.9 V at VDD = 5 V – 2.3 V at VDD = 10 V – 3.5 V at VDD = 15 V • Noise Immunity Greater Than 50% • No Limit On Input Rise and Fall Times • Standardized, Symmetrical Output Characteristics • For Quiescent Current at

丝印代码：CM0107；CMOS Dual 2-Input NAND Buffer/Driver

Features: 32 times standard B-Series output current drive sinking capability — 136 mA typ. Vpp=10V,Vps=1V 100% tested for quiescent current at 20 V. Maximum input current of 1 uA at 18 over full package-temperature range; 100 nA at 18 V and 25°C 5-V, 10-V, and 15-V parametric ratin

丝印代码：CM0107；CMOS Dual 2-Input NAND Buffer/Driver

Features: 32 times standard B-Series output current drive sinking capability — 136 mA typ. Vpp=10V,Vps=1V 100% tested for quiescent current at 20 V. Maximum input current of 1 uA at 18 over full package-temperature range; 100 nA at 18 V and 25°C 5-V, 10-V, and 15-V parametric ratin

丝印代码：CM0107；CMOS Dual 2-Input NAND Buffer/Driver

Features: 32 times standard B-Series output current drive sinking capability — 136 mA typ. Vpp=10V,Vps=1V 100% tested for quiescent current at 20 V. Maximum input current of 1 uA at 18 over full package-temperature range; 100 nA at 18 V and 25°C 5-V, 10-V, and 15-V parametric ratin

丝印代码：CM0107；CMOS Dual 2-Input NAND Buffer/Driver

Features: 32 times standard B-Series output current drive sinking capability — 136 mA typ. Vpp=10V,Vps=1V 100% tested for quiescent current at 20 V. Maximum input current of 1 uA at 18 over full package-temperature range; 100 nA at 18 V and 25°C 5-V, 10-V, and 15-V parametric ratin

丝印代码：CM0107B；CMOS Dual 2-Input NAND Buffer/Driver

Features: 32 times standard B-Series output current drive sinking capability — 136 mA typ. Vpp=10V,Vps=1V 100% tested for quiescent current at 20 V. Maximum input current of 1 uA at 18 over full package-temperature range; 100 nA at 18 V and 25°C 5-V, 10-V, and 15-V parametric ratin

丝印代码：CM0107B；CMOS Dual 2-Input NAND Buffer/Driver

Features: 32 times standard B-Series output current drive sinking capability — 136 mA typ. Vpp=10V,Vps=1V 100% tested for quiescent current at 20 V. Maximum input current of 1 uA at 18 over full package-temperature range; 100 nA at 18 V and 25°C 5-V, 10-V, and 15-V parametric ratin

丝印代码：CM0107B；CMOS Dual 2-Input NAND Buffer/Driver

Features: 32 times standard B-Series output current drive sinking capability — 136 mA typ. Vpp=10V,Vps=1V 100% tested for quiescent current at 20 V. Maximum input current of 1 uA at 18 over full package-temperature range; 100 nA at 18 V and 25°C 5-V, 10-V, and 15-V parametric ratin

丝印代码：CM0107B；CMOS Dual 2-Input NAND Buffer/Driver

Features: 32 times standard B-Series output current drive sinking capability — 136 mA typ. Vpp=10V,Vps=1V 100% tested for quiescent current at 20 V. Maximum input current of 1 uA at 18 over full package-temperature range; 100 nA at 18 V and 25°C 5-V, 10-V, and 15-V parametric ratin

丝印代码：CM0107B；CMOS Dual 2-Input NAND Buffer/Driver

Features: 32 times standard B-Series output current drive sinking capability — 136 mA typ. Vpp=10V,Vps=1V 100% tested for quiescent current at 20 V. Maximum input current of 1 uA at 18 over full package-temperature range; 100 nA at 18 V and 25°C 5-V, 10-V, and 15-V parametric ratin

丝印代码：CM0109B；CMOS Quad Low-to-High Voltage Level Shifter

Features: Independence of power supply sequence considerations—V cc can exceed Vp, input signals can exceed both Ve and Vpp Up and down level-shifting capability Three-state outputs with seperate enable controls Standardized, symmetrical output characteristics 100% tested for quiescent

丝印代码：CM0109B；CMOS Quad Low-to-High Voltage Level Shifter

Features: Independence of power supply sequence considerations—V cc can exceed Vp, input signals can exceed both Ve and Vpp Up and down level-shifting capability Three-state outputs with seperate enable controls Standardized, symmetrical output characteristics 100% tested for quiescent

丝印代码：CM0109B；CMOS Quad Low-to-High Voltage Level Shifter

Features: Independence of power supply sequence considerations—V cc can exceed Vp, input signals can exceed both Ve and Vpp Up and down level-shifting capability Three-state outputs with seperate enable controls Standardized, symmetrical output characteristics 100% tested for quiescent

丝印代码：CM0109B；CMOS Quad Low-to-High Voltage Level Shifter

Features: Independence of power supply sequence considerations—V cc can exceed Vp, input signals can exceed both Ve and Vpp Up and down level-shifting capability Three-state outputs with seperate enable controls Standardized, symmetrical output characteristics 100% tested for quiescent

丝印代码：CM0109B；CMOS Quad Low-to-High Voltage Level Shifter

Features: Independence of power supply sequence considerations—V cc can exceed Vp, input signals can exceed both Ve and Vpp Up and down level-shifting capability Three-state outputs with seperate enable controls Standardized, symmetrical output characteristics 100% tested for quiescent

丝印代码：CM0109B；CMOS Quad Low-to-High Voltage Level Shifter

Features: Independence of power supply sequence considerations—V cc can exceed Vp, input signals can exceed both Ve and Vpp Up and down level-shifting capability Three-state outputs with seperate enable controls Standardized, symmetrical output characteristics 100% tested for quiescent

丝印代码：CM0109B；CMOS Quad Low-to-High Voltage Level Shifter

Features: Independence of power supply sequence considerations—V cc can exceed Vp, input signals can exceed both Ve and Vpp Up and down level-shifting capability Three-state outputs with seperate enable controls Standardized, symmetrical output characteristics 100% tested for quiescent

丝印代码：CM010B；CMOS Hex Buffers/Converters

Features: = 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C 5.V, 10-V, and 15-V parametric ratings

丝印代码：CM010B；CMOS Hex Buffers/Converters

Features: = 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C 5.V, 10-V, and 15-V parametric ratings

丝印代码：CM010B；CMOS Hex Buffers/Converters

Features: = 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C 5.V, 10-V, and 15-V parametric ratings

丝印代码：CM010B；CMOS Hex Buffers/Converters

Features: = 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C 5.V, 10-V, and 15-V parametric ratings

丝印代码：CM010B；CMOS Hex Buffers/Converters

Features: = 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C 5.V, 10-V, and 15-V parametric ratings

丝印代码：CM011B；CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

丝印代码：CM011B；CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

丝印代码：CM011B；CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

丝印代码：CM011B；CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

丝印代码：CM011UB；CMOS Quad 2-Input NAND Gate

Features: Propagation delay time = 30 ns (typ). at CL=50pF, Vpp=10V Standardized symmetrical output characteristics = 100% tested for quiescent current at 20V Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 5.V, 10-V, and 15-V p

丝印代码：CM011UB；CMOS Quad 2-Input NAND Gate

Features: Propagation delay time = 30 ns (typ). at CL=50pF, Vpp=10V Standardized symmetrical output characteristics = 100% tested for quiescent current at 20V Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 5.V, 10-V, and 15-V p

丝印代码：CM012B；CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

丝印代码：CM012B；CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

丝印代码：CM015B；CMOS Dual 4-Stage Static Shift Register

Features: & Medium speed operation ............. 12 MHz (typ.) clock rate at Vpp — Vg = 10 V ® Fully static operation 8 master-slave flip-flops plus input and output buffering # 100% tested for quiescent current at 20 V #5.V,10-V, and 15-V parametric ratings = Standardized, symmetrical

丝印代码：CM015B；CMOS Dual 4-Stage Static Shift Register

Features: ® Medium speed operation . ............ 12 MHz (typ.) clock rate at Vpp — Vgg = 10 V ® Fully static operation ® 8 master-slave flip-flops plus input and output buffering ® 100% tested for quiescent current at 20 V ®5.V, 10-V, and 15-V parametric ratings ® Standardized, symmetr

丝印代码：CM015B；CMOS Dual 4-Stage Static Shift Register

Features: & Medium speed operation ............. 12 MHz (typ.) clock rate at Vpp — Vg = 10 V ® Fully static operation 8 master-slave flip-flops plus input and output buffering # 100% tested for quiescent current at 20 V #5.V,10-V, and 15-V parametric ratings = Standardized, symmetrical

丝印代码：CM015B；CMOS Dual 4-Stage Static Shift Register

Features: ® Medium speed operation . ............ 12 MHz (typ.) clock rate at Vpp — Vgg = 10 V ® Fully static operation ® 8 master-slave flip-flops plus input and output buffering ® 100% tested for quiescent current at 20 V ®5.V, 10-V, and 15-V parametric ratings ® Standardized, symmetr

丝印代码：CM015B；CMOS Dual 4-Stage Static Shift Register

Features: ® Medium speed operation . ............ 12 MHz (typ.) clock rate at Vpp — Vgg = 10 V ® Fully static operation ® 8 master-slave flip-flops plus input and output buffering ® 100% tested for quiescent current at 20 V ®5.V, 10-V, and 15-V parametric ratings ® Standardized, symmetr

丝印代码：CM0161B；CMOS Synchronous Programmable 4-Bit Counters

Features: Internal look-ahead for fast counting Carry output for cascading Synchronously programmable Clear asynchronous input {CD40160B, CD40161B) Clear synchronous input (CD40162B, CD40163B) Synchronous load control input Bm Low-power TTL compatibility m Standardized, symmetrical

丝印代码：CM0161B；CMOS Synchronous Programmable 4-Bit Counters

Features: Internal look-ahead for fast counting Carry output for cascading Synchronously programmable Clear asynchronous input {CD40160B, CD40161B) Clear synchronous input (CD40162B, CD40163B) Synchronous load control input Bm Low-power TTL compatibility m Standardized, symmetrical

丝印代码：CM0174B；CMOS Hex D - Type Flip-Flop

Features: 5.V, 10-V, and 15-V parametric rating Standsrdized symmetrical output characteristics 100% tested for quiescent current at 20 V Maximum input current of 1 pA at 18 V . over full peckage-temperature range; 100 nA at 18 Vand 25°C Noise margin (over full package-temperature ran

丝印代码：CM0174B；CMOS Hex D - Type Flip-Flop

Features: 5.V, 10-V, and 15-V parametric rating Standsrdized symmetrical output characteristics 100% tested for quiescent current at 20 V Maximum input current of 1 pA at 18 V . over full peckage-temperature range; 100 nA at 18 Vand 25°C Noise margin (over full package-temperature ran

丝印代码：CM0175B；CMOS Quad D - Type Flip-Flop

Features: 100% tested for quiescent current at20v Maximum input current of 1 uA at 18 V over full package- temperature range; 100.nA at 18V and 25°C | Noise margin (full package- temperature range) = 1VatVoo=5V 2VatVop=10V 25VatVoo=15V 5-V, 10-V, and 15-V parametric ratings Meets

丝印代码：CM0175B；CMOS Quad D - Type Flip-Flop

Features: 100% tested for quiescent current at20v Maximum input current of 1 uA at 18 V over full package- temperature range; 100.nA at 18V and 25°C | Noise margin (full package- temperature range) = 1VatVoo=5V 2VatVop=10V 25VatVoo=15V 5-V, 10-V, and 15-V parametric ratings Meets

丝印代码：CM017B；CMOS Counter/Dividers

Features: Fully static operation = Medium-speed operation . . 10 MHz (typ) at Vpp = 10 V Standardized, symmetrical output characteristics 100% tested for quiescent current at 20 V 5-V,10V, and 15-V parametric ratings Meets all requirements of JEDEC Tentative Standard No. 134, “St

丝印代码：CM017B；CMOS Counter/Dividers

Features: Fully static operation = Medium-speed operation . . 10 MHz (typ) at Vpp = 10 V Standardized, symmetrical output characteristics 100% tested for quiescent current at 20 V 5-V,10V, and 15-V parametric ratings Meets all requirements of JEDEC Tentative Standard No. 134, “St

丝印代码：CM017B；CMOS Counter/Dividers

Features: Fully static operation = Medium-speed operation . . 10 MHz (typ) at Vpp = 10 V Standardized, symmetrical output characteristics 100% tested for quiescent current at 20 V 5-V,10V, and 15-V parametric ratings Meets all requirements of JEDEC Tentative Standard No. 134, “St

丝印代码：CM017B；CMOS Counter/Dividers

Features: Fully static operation = Medium-speed operation . . 10 MHz (typ) at Vpp = 10 V Standardized, symmetrical output characteristics 100% tested for quiescent current at 20 V 5-V,10V, and 15-V parametric ratings Meets all requirements of JEDEC Tentative Standard No. 134, “St

丝印代码：CM018B；CMOS Presettable Divide-By-N Counter

Features: Medium speed operation. . . . . .10MHz (typ. at Vpp - Vs = 10V Fully static operation = 100% tested for quiescent current at 20 V = Standardized, symmetrical output characteristics = 5-V, 10-V, and 15-V parametric ratings Maximum input current of 1 uA at 18 V over full pack

丝印代码：CM018B；CMOS Presettable Divide-By-N Counter

Features: Medium speed operation. . . . . .10MHz (typ. at Vpp - Vs = 10V Fully static operation = 100% tested for quiescent current at 20 V = Standardized, symmetrical output characteristics = 5-V, 10-V, and 15-V parametric ratings Maximum input current of 1 uA at 18 V over full pack

丝印代码：CM0193B；CMOS Presettable Up/Down Counters (Dual Clock With Reset)

Features: Individual clock lines for counting up or counting down Synchronous high-speed carry and borrow propagation delays for cascading Asynchronous reset and preset capability Medium-speed operation—fcy = 8 MHz (typ) @ 10 V 5.V, 10-V, and 15-V parametric ratings Standardized, symmetrica

丝印代码：CM0193B；CMOS Presettable Up/Down Counters (Dual Clock With Reset)

Features: Individual clock lines for counting up or counting down Synchronous high-speed carry and borrow propagation delays for cascading Asynchronous reset and preset capability Medium-speed operation—fcy = 8 MHz (typ) @ 10 V 5.V, 10-V, and 15-V parametric ratings Standardized, symmetrica

丝印代码：CM0193B；CMOS Presettable Up/Down Counters (Dual Clock With Reset)

Features: Individual clock lines for counting up or counting down Synchronous high-speed carry and borrow propagation delays for cascading Asynchronous reset and preset capability Medium-speed operation—fcy = 8 MHz (typ) @ 10 V 5.V, 10-V, and 15-V parametric ratings Standardized, symmetrica

丝印代码：CM019B；CMOS Quaa AND/OR Select Gate High-Voltage Types (20-Volt Rating)

Features: 8 Medium-speed operation... .. + -tpHL = tp Ly = 60 ns (typ.) at C) =50pF,Vpp=10V Standardized, symmetrical output characteristics 100% tested for quiescent current at 20 V 5-V, 10-V, and 15-V parametric ratings Meets all requirements of JEDEC Tentative Standard No. 138, “S

丝印代码：CM019B；CMOS Quaa AND/OR Select Gate High-Voltage Types (20-Volt Rating)

Features: 8 Medium-speed operation... .. + -tpHL = tp Ly = 60 ns (typ.) at C) =50pF,Vpp=10V Standardized, symmetrical output characteristics 100% tested for quiescent current at 20 V 5-V, 10-V, and 15-V parametric ratings Meets all requirements of JEDEC Tentative Standard No. 138, “S