适用于 DRAM 应用且具有 10 个输出的 3.3V 锁相环路时钟驱动器

The CDCVF2510 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The • Designed to Meet and Exceed PC133 SDRAM Registered DIMM Specification Rev. 1.1\n• Operating Frequency 50 MHz to 175 MHz\n• Jitter (cyc - cyc) at 66 MHz to 166 MHz Is |70| ps\n• Available in Plastic 24-Pin TSSOP\n• Distributes One Clock Input to One Bank of 10 Outputs\n• 25- On-Chip Series Damping ;

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

文件：766.76 Kbytes Page：16 Pages

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

文件：144.16 Kbytes Page：11 Pages

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

文件：764.4 Kbytes Page：16 Pages

具有断电模式的 3.3V 锁相环路时钟驱动器

The CDCVF2510A is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. The CDCVF2510A uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchrono • Designed to Meet and Exceed PC133 SDRAM Registered DIMM Specification Rev. 1.1\n• Spread Spectrum Clock Compatible\n• Operating Frequency 20 MHz to 175 MHz\n• Static Phase Error Distribution at 66 MHz to 166 MHz is ±125 ps\n• Jitter (cyc–cyc) at 66 MHz to 166 MHz is |70| ps\n• Advanced Deep Submic;

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

文件：766.76 Kbytes Page：16 Pages

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

文件：764.4 Kbytes Page：16 Pages

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE

文件：557.49 Kbytes Page：18 Pages

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE

文件：166.43 Kbytes Page：13 Pages

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE

文件：551.76 Kbytes Page：17 Pages

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE

文件：557.49 Kbytes Page：18 Pages

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE

文件：557.49 Kbytes Page：18 Pages

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE

文件：557.49 Kbytes Page：18 Pages

封装/外壳：24-TSSOP（0.173"，4.40mm 宽） 包装：卷带（TR） 描述：IC 3.3V PLL CLK-DRVR 24-TSSOP 集成电路（IC） 时钟发生器，PLL，频率合成器

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE

文件：557.49 Kbytes Page：18 Pages

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE

文件：551.76 Kbytes Page：17 Pages

封装/外壳：24-TSSOP（0.173"，4.40mm 宽） 包装：卷带（TR） 描述：IC 3.3V PLL CLK-DRVR 24-TSSOP 集成电路（IC） 时钟发生器，PLL，频率合成器

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE

文件：557.49 Kbytes Page：18 Pages

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

文件：766.76 Kbytes Page：16 Pages

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

文件：764.4 Kbytes Page：16 Pages

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

文件：144.16 Kbytes Page：11 Pages

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

文件：766.76 Kbytes Page：16 Pages

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

文件：764.4 Kbytes Page：16 Pages

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

文件：766.76 Kbytes Page：16 Pages

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

文件：764.4 Kbytes Page：16 Pages

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

文件：766.76 Kbytes Page：16 Pages

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

文件：764.4 Kbytes Page：16 Pages

Lamps for Photolithography

Description PerkinElmer Optoelectronics is a leading manufacturer of mercury short arc lamps ranging in output power from 1000 to 8000 watts. These lamps are used in the production of printed circuit boards, liquid crystal displays and semiconductors. The HSH Series lamps are used worldwide in mi

Lamps for Photolithography

Description PerkinElmer Optoelectronics is a leading manufacturer of mercury short arc lamps ranging in output power from 1000 to 8000 watts. These lamps are used in the production of printed circuit boards, liquid crystal displays and semiconductors. The HSH Series lamps are used worldwide in mi

Silicon NPNTransistor High Frequency Video Output

Features: • High Gain Bandwidth Product: fT = 2GHz • High Current Capacity: IC = 500mA Applications: • High–Definition CRT Display Video Output • Wide–Band Amp

50-150 MHz 1:10 SDRAM clock driver

DESCRIPTION The PCK2510SA is a high-performance, low-skew, low-jitter, phase-locked loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The

50-150 MHz 1:10 SDRAM clock driver

DESCRIPTION The PCK2510S is a high-performance, low-skew, low-jitter, phase-locked loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The P