PROGRAMMABLE 3-PLL CLOCK SYNTHESIZER/MULTIPLIER/DIVIDER

1FEATURES · High-Performance 3:6 PLL-Based Clock Synthesizer/Multiplier/Divider · User-Programmable PLL Frequencies · EEPROM Programming Without the Need to Apply High Programming Voltage · Easy In-Circuit Programming via SMBus Data Interface · Wide PLL Divider Ratio Allows 0-ppm Output C

PROGRAMMABLE 3-PLL CLOCK SYNTHESIZER / MULTIPLIER / DIVIDER

文件：1.64453 Mbytes Page：32 Pages

PROGRAMMABLE 3-PLL CLOCK SYNTHESIZER/MULTIPLIER/DIVIDER

文件：1.030829 Mbytes Page：40 Pages

300MHz、LVCMOS、可编程 3-PLL 时钟合成器/倍频器/分频器

PROGRAMMABLE 3-PLL CLOCK SYNTHESIZER/MULTIPLIER/DIVIDER

1FEATURES · High-Performance 3:6 PLL-Based Clock Synthesizer/Multiplier/Divider · User-Programmable PLL Frequencies · EEPROM Programming Without the Need to Apply High Programming Voltage · Easy In-Circuit Programming via SMBus Data Interface · Wide PLL Divider Ratio Allows 0-ppm Output C

PROGRAMMABLE 3-PLL CLOCK SYNTHESIZER/MULTIPLIER/DIVIDER

1FEATURES · High-Performance 3:6 PLL-Based Clock Synthesizer/Multiplier/Divider · User-Programmable PLL Frequencies · EEPROM Programming Without the Need to Apply High Programming Voltage · Easy In-Circuit Programming via SMBus Data Interface · Wide PLL Divider Ratio Allows 0-ppm Output C

PROGRAMMABLE 3-PLL CLOCK SYNTHESIZER/MULTIPLIER/DIVIDER

1FEATURES · High-Performance 3:6 PLL-Based Clock Synthesizer/Multiplier/Divider · User-Programmable PLL Frequencies · EEPROM Programming Without the Need to Apply High Programming Voltage · Easy In-Circuit Programming via SMBus Data Interface · Wide PLL Divider Ratio Allows 0-ppm Output C

PROGRAMMABLE 3-PLL CLOCK SYNTHESIZER/MULTIPLIER/DIVIDER

1FEATURES · High-Performance 3:6 PLL-Based Clock Synthesizer/Multiplier/Divider · User-Programmable PLL Frequencies · EEPROM Programming Without the Need to Apply High Programming Voltage · Easy In-Circuit Programming via SMBus Data Interface · Wide PLL Divider Ratio Allows 0-ppm Output C

PROGRAMMABLE 3-PLL CLOCK SYNTHESIZER/MULTIPLIER/DIVIDER

1FEATURES · High-Performance 3:6 PLL-Based Clock Synthesizer/Multiplier/Divider · User-Programmable PLL Frequencies · EEPROM Programming Without the Need to Apply High Programming Voltage · Easy In-Circuit Programming via SMBus Data Interface · Wide PLL Divider Ratio Allows 0-ppm Output C

PROGRAMMABLE 3-PLL CLOCK SYNTHESIZER/MULTIPLIER/DIVIDER

1FEATURES · High-Performance 3:6 PLL-Based Clock Synthesizer/Multiplier/Divider · User-Programmable PLL Frequencies · EEPROM Programming Without the Need to Apply High Programming Voltage · Easy In-Circuit Programming via SMBus Data Interface · Wide PLL Divider Ratio Allows 0-ppm Output C

PROGRAMMABLE 3-PLL CLOCK SYNTHESIZER/MULTIPLIER/DIVIDER

文件：1.030829 Mbytes Page：40 Pages

PROGRAMMABLE 3-PLL CLOCK SYNTHESIZER/MULTIPLIER/DIVIDER

文件：1.030829 Mbytes Page：40 Pages

PROGRAMMABLE 3-PLL CLOCK SYNTHESIZER/MULTIPLIER/DIVIDER

文件：1.030829 Mbytes Page：40 Pages

封装/外壳：20-TSSOP（0.173"，4.40mm 宽） 包装：卷带（TR） 描述：IC 3-PLL SYNTH/MULT/DIV 20-TSSOP 集成电路（IC） 时钟发生器，PLL，频率合成器

封装/外壳：20-TSSOP（0.173"，4.40mm 宽） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC 3-PLL SYNTH/MULT/DIV 20-TSSOP 集成电路（IC） 时钟发生器，PLL，频率合成器

PROGRAMMABLE 3-PLL CLOCK SYNTHESIZER/MULTIPLIER/DIVIDER

文件：1.030829 Mbytes Page：40 Pages

PROGRAMMABLE 3-PLL CLOCK SYNTHESIZER/MULTIPLIER/DIVIDER

文件：1.030829 Mbytes Page：40 Pages

WIRE & CABLE TERMINATION

文件：3.92843 Mbytes Page：50 Pages

Stacking Header Set for Beagle Bone Capes

文件：219.46 Kbytes Page：2 Pages

RoHS-Compliant Commencing With 10/1/2004 Production

文件：379.36 Kbytes Page：2 Pages

One-Piece Surface Steel Raceway

文件：290.29 Kbytes Page：8 Pages

One-Piece Surface Steel Raceway

文件：290.29 Kbytes Page：8 Pages