具有 LVPECL 输出和 LVTTL 输出以及 1/2x、1x 和 2x 频率选项的 3.3V PLL 时钟驱动器

The CDC582 is a high-performance, low-skew, low-jitter clock driver. It uses a phase-lock loop (PLL) to precisely align the frequency and phase of the clock output signals to the differential LVPECL clock (CLKIN, ) input signals. It is specifically designed to operate at speeds from 50 MHz to 100 MH ·Low Output Skew for Clock-Distribution and Clock-GenerationApplications·Operates at 3.3-V VCC·Distributes Differential LVPECL Clock Inputs to 12TTL-Compatible Outputs·Two Select Inputs Configure Up to Nine Outputs to Operate atOne-Half or Double the Input Frequency·No External RC Network Required·S;

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH DIFFERENTIAL LVPECL CLOCK INPUTS

文件：143.57 Kbytes Page：10 Pages

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

文件：150.07 Kbytes Page：10 Pages

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

文件：150.07 Kbytes Page：10 Pages

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH DIFFERENTIAL LVPECL CLOCK INPUTS

文件：143.57 Kbytes Page：10 Pages

封装/外壳：52-TQFP 包装：管件 描述：IC 3.3V PLL CLOCK DRIVER 52-TQFP 集成电路（IC） 时钟发生器，PLL，频率合成器

封装/外壳：52-TQFP 包装：卷带（TR） 描述：IC 3.3V PLL CLOCK DRIVER 52-TQFP 集成电路（IC） 时钟发生器，PLL，频率合成器

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

文件：150.07 Kbytes Page：10 Pages

Low Cost Sample/Hold Amplifier

PRODUCT DESCRIPTION The AD582 is a low cost integrated circuit sample and hold amplifier consisting of a high performance operational amplifier, a low leakage analog switch and a JFET integrating amplifier - all fabricated on a single monolithic chip. An external holding capacitor, connected to t

Silicon RF Switching Diode

● For low-loss VHF band switching in TV/VTR tuners

Two Channel Direct Drive Speech Controller?

INTRODUCTION SNC582 is a two-channel voice synthesizer IC with PWM direct drive circuit. It built-in a 4-bit tiny controller with one 4-bit input port and two 4-bit I/O ports. By programming through the tiny controller in SNC582, user’s varied applications including voice section combination, key