丝印代码：CDC329A；1-LINE TO 6-LINE CLOCK DRIVER WITH SELECTABLE POLARITY

Low Output Skew for Clock-Distribution and Clock-Generation Applications TTL-Compatible Inputs and CMOS-Compatible Outputs Distributes One Clock Input to Six Clock Outputs Polarity Control Selects True or Complementary Outputs Distributed VCC and GND Pins Reduce Switching Noise High-Driv

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 包装：卷带（TR） 描述：IC CLK BUFFER 1:6 80MHZ 16SOIC 集成电路（IC） 时钟缓冲器，驱动器

1Line to 6Line Clock Driver

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