具有 1/2x、1x 及 2x 频率选项的 3.3V PLL 时钟驱动器

The CDC2586 is a high-performance, low-skew, low-jitter clock driver. It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the clock output signals to the clock input (CLKIN) signal. It is specifically designed for use with popular microprocessors operating at speeds from ·Low Output Skew for Clock-Distribution and Clock-Generation Applications ·Operates at 3.3-V VCC ·Distributes One Clock Input to 12 Outputs ·Two Select Inputs Configure Up to Nine Outputs to Operate at One-Half or Double the Input Frequency ·No External RC Network Required ·External Feedback (FBIN);

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

文件：307.16 Kbytes Page：14 Pages

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS

文件：165.85 Kbytes Page：12 Pages

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

文件：307.16 Kbytes Page：14 Pages

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

文件：307.16 Kbytes Page：14 Pages

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS

文件：165.85 Kbytes Page：12 Pages

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

文件：307.16 Kbytes Page：14 Pages

封装/外壳：52-TQFP 包装：卷带（TR） 描述：IC 3.3V PLL CLK-DRVR 52-TQFP 集成电路（IC） 时钟发生器，PLL，频率合成器

封装/外壳：52-TQFP 包装：卷带（TR） 描述：IC 3.3V PLL CLK-DRVR 52-TQFP 集成电路（IC） 时钟发生器，PLL，频率合成器

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

文件：307.16 Kbytes Page：14 Pages

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

文件：307.16 Kbytes Page：14 Pages

Silicon NPN Transistor High Voltage, High Speed Switch

Features: ● High Breakdown Voltage, High Reliability ● Fast Switching Speed ● Wide ASO Range

SIMPLE SWITCHER 3A Flyback Regulator with Shutdown

文件：778.87 Kbytes Page：28 Pages

SIMPLE SWITCHER 3A Flyback Regulator with Shutdown

文件：778.87 Kbytes Page：28 Pages