High-Speed CMOS Logic 4-Bit Parallel Access Register

Features • Asynchronous Master Reset • J, K, (D) Inputs to First Stage • Fully Synchronous Serial or Parallel Data Transfer • Shift Right and Parallel Load Capability • Complementary Output From Last Stage • Buffered Inputs • Typical fMAX = 50MHz at VCC = 5V, CL = 15pF, TA = 25oC • Fanout

封装/外壳：16-TSSOP（0.173"，4.40mm 宽） 功能：通用 包装：管件 描述：IC 4-BIT ACCESS REGISTER 16TSSOP 集成电路（IC） 移位寄存器

High-Speed CMOS Logic 4-Bit Parallel Access Register

文件：335.19 Kbytes Page：11 Pages

High-Speed CMOS Logic 4-Bit Parallel Access Register

文件：341.18 Kbytes Page：13 Pages

High-Speed CMOS Logic 4-Bit Parallel Access Register

文件：632.02 Kbytes Page：16 Pages

High Speed CMOS Logic 4-Bit Parallel Access Register

文件：42.23 Kbytes Page：6 Pages

High-Speed CMOS Logic 4-Bit Parallel Access Register

文件：335.19 Kbytes Page：11 Pages

High-Speed CMOS Logic 4-Bit Parallel Access Register

文件：341.18 Kbytes Page：13 Pages

High-Speed CMOS Logic 4-Bit Parallel Access Register

文件：632.02 Kbytes Page：16 Pages

High-Speed CMOS Logic 4-Bit Parallel Access Register

文件：632.02 Kbytes Page：16 Pages

High-Speed CMOS Logic 4-Bit Parallel Access Register

文件：341.18 Kbytes Page：13 Pages

High-Speed CMOS Logic 4-Bit Parallel Access Register

文件：632.02 Kbytes Page：16 Pages

4-bit parallel access shift register

GENERAL DESCRIPTION The 74HC/HCT195 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Asynchronous master reset • J,K, (D) inputs to the first stage • Fully syn